Method of fabricating a bottom electrode

Details Method of fabricating a bottom electrode Method of fabricating a bottom electrode

2000-11-01

2001-11-13

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

Reexamination Certificate

active

06316352

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89122368, filed Oct. 24, 2000.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor fabrication method. More particularly, the present invention relates to a method of fabricating a bottom electrode.
2. Description of the Related Art
As the integration of the semiconductor devices increases and the linewidth thereof decreases, it becomes desirable to form more semiconductor devices in a very limited area. Due to limitations imposed by the fabrication process, it is difficult to achieve a highly integrated circuit. In addition, because difficulties exist in forming a highly integrated device, it is hard to ensure the reliability of the device. Therefore, how to fabricate highly integrated semiconductor devices has became the main topic of the recent research on semiconductor fabrication at the 0.13 micron level.
FIG. 1
is a schematic, cross-sectional view illustrating a conventional method of forming a bit line and a bottom electrode.
A metal oxide semiconductor (MOS) is formed on the substrate
100
. The MOS includes a gate
102
on the substrate
100
, a spacer
104
on the sidewall of the gate
102
and the source/drain region
106
in the substrate
100
beside the gate
102
. A dielectric layer
108
is formed over the substrate
100
to cover the MOS. A bit line
110
is formed through the dielectric layer
108
to electrically couple with the source/drain region
106
. A dielectric layer
112
is formed over the substrate
100
to cover the bit line
110
. A bottom electrode
114
is formed through the dielectric layers
108
and
112
to electrically couple with the source/drain region
106
.
In the conventional method, devices, such as bit line
110
and the bottom electrode
114
are separated from each other. Consequently, the integration of the semiconductor circuit cannot be effectively increased. Thus, there is a need to further increase the integration of semiconductor devices.
In addition, due to the fabrication limitation for forming semiconductor devices in a limited area, box-shaped capacitors are usually formed. However, the conventional box-shaped capacitor cannot provide sufficient capacitance. Thus, the capacitance of the conventional capacitor is limited.
SUMMARY OF THE INVENTION
The invention provides a method of fabricating a bottom electrode. A substrate having a first conductive layer therein is provided. A first dielectric layer is formed over the substrate. A plurality bit lines is formed over the first dielectric layer. A conformal liner layer is formed over the first dielectric layer to cover the plurality bit lines. A second dielectric layer is formed over the conformal liner layer. An opening is formed in the second dielectric layer. The opening exposes a portion of the conformal liner layer between the bit lines and the conformal liner layer on portions of the bit lines. A conductive spacer is formed on a sidewall of the opening to expose a portion of the conformal liner layer between the bit lines. The exposed portion of the conformal liner layer between the bit lines is removed. The first dielectric layer exposed by the conductive spacer and the second dielectric layer are removed. A node contact opening is formed in the first dielectric layer to expose the conductive layer. A second conductive layer is formed to fill the node contact opening.
In contrast with the conventional method, which has devices far way from each other, the devices of the present invention are next to each other. In addition, since the liner layer is used to isolate the bit lines from the bottom electrode, the reliability of the devices is enhanced. Furthermore, in comparison with the box-shaped bottom electrode formed by the conventional method, the bottom electrode of the present invention has an increased surface area.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5966610 (1999-10-01), Wang et al.
patent: 6054394 (2000-04-01), Wang

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