Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-07-08
2001-02-20
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S627000, C438S633000, C438S637000, C438S640000, C438S672000, C438S687000
Reexamination Certificate
active
06191025
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method of forming a copper damascene structure over a filled contact hole and more particularly to the use of a sacrificial dielectric layer to protect an etch stop layer during chemical mechanical polishing.
2. Description of the Related Art
As the cross section area of conductors in integrated circuits continue to shrink the conductivity of the conductor material becomes increasingly important. While aluminum has long been the conductor material of choice in integrated circuits, materials having greater conductivity such as gold, silver, copper, or the like are used with increasing frequency.
These metals have not had more widespread use because they suffer from a number of disadvantages such as the formation of undesirable intermetallics and high diffusion rates. Copper has the additional disadvantage of being easily oxidized at relatively low temperatures. One particular problem of this easy oxidation of copper is that conventional photoresist processing can not be used to pattern the copper. At the end of the patterning process using photoresist the photoresist must be removed by heating it in a highly oxidizing environment which also oxidizes the copper conductors. One solution to this problem is the Damascene process for forming conductors.
U.S. Pat. No. 5,744,376 to Chan et al. describes a method of forming copper interconnections using a damascene structure with provisions to prevent both copper diffusion and copper oxidation.
U.S. Pat. No. 5,693,563 to Teong describes a method of forming copper interconnections using an etch stop in a double damascene structure having provision to prevent both copper diffusion and oxidation.
U.S. Pat. No. 5,817,572 to Chiang et al. describes a method of forming copper damascene structures using etch stop layers and barrier layers to prevent copper diffusion and oxidation.
U.S. Pat. No. 5,612,254 to Mu et al. also describes a method of forming copper damascene structures using etch stop layers and barrier layers to prevent copper diffusion and oxidation.
Patent application Ser. No. 09/349,849 (TSMC-98-494), Filed Jul. 8, 1999, entitled “ROBUST POST Cu-CMP IMD PROCESS” and assigned to the same Assignee describes methods of cleaning exposed copper between the steps of chemical mechanical polishing and intermetal dielectric deposition.
Patent application Ser. No. 09/374,309 (TSMC-98-495), Filed Aug. 16, 1999, entitled “PASSIVATION METHOD FOR COPPER PROCESS” and assigned to the same Assignee describes methods of passivation of exposed copper in a copper damascene structure.
SUMMARY OF THE INVENTION
Forming damascene conductor structures using copper or other conducting materials requires the deposition of a layer of trench dielectric. A trench is then etched in the layer of trench dielectric to define the shape of the conductor. A layer of barrier metal is then deposited over the trench dielectric, on the sidewalls of the trench, and on the bottom of the trench. A conductor metal, such as copper, is then deposited on the layer of barrier metal to more than fill the trench. The barrier metal and conductor metal are then removed down to the level of the trench dielectric, usually using a method such as chemical mechanical polishing, to define the conductor.
Frequently the damascene structure is formed on top of a layer of interlevel dielectric or intermetal dielectric. The layer of interlevel dielectric or intermetal dielectric may have contact holes which are filled with conducting plugs. The damascene structure may form electrical contact with the conducting plugs filling the contact holes in the interlevel dielectric or intermetal dielectric. The layer of interlevel dielectric or intermetal dielectric usually has a layer of barrier dielectric formed thereon to act as an etch stop and protect the interlevel dielectric or intermetal dielectric during the formation of the damascene structure. The conducting plugs are formed by depositing one or more metals to more than fill the contact holes followed by chemical mechanical polishing to define the contact hole plugs. A key problem frequently encountered is damage to the layer of barrier dielectric during the chemical mechanical polishing step used to define the contact hole plugs. A sufficiently damaged layer of barrier dielectric will not perform satisfactorily as an etch stop.
It is a principle objective of this invention to provide a method of forming a damascene conductor structure over a layer of intermetal dielectric and a layer of barrier dielectric having contact plugs making electrical contact with the conductor of the damascene structure which does not damage the barrier dielectric.
It is another principle objective of this invention to provide a method of forming a damascene conductor structure over a layer of interlevel dielectric and a layer of barrier dielectric which does not damage the barrier dielectric.
These objectives are achieved by the use of a layer of sacrificial dielectric deposited on the layer of barrier dielectric. The chemical mechanical polishing step can remove a part of the layer of sacrificial dielectric without damaging the layer of barrier dielectric.
REFERENCES:
patent: 5612254 (1997-03-01), Mu et al.
patent: 5693563 (1997-12-01), Teong
patent: 5741626 (1998-04-01), Jain et al.
patent: 5744376 (1998-04-01), Chan et al.
patent: 5817572 (1998-10-01), Chiang et al.
patent: 5821168 (1998-10-01), Jain
patent: 5880018 (1999-03-01), Boeck et al.
patent: 6054398 (2000-04-01), Pamanick
patent: 6100181 (2000-08-01), You et al.
patent: 6107185 (2000-08-01), Lukanc
Liu Chung-Shi
Yu Chen-Hua
Ackerman Stephen B.
Bowers Charles
Nguyen Thanh
Prescott Larry J.
Saile George O.
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