Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2000-03-17
2001-02-20
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000, C365S222000, C365S230030
Reexamination Certificate
active
06191985
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
Dynamic random access memories (DRAMs) are customarily organized in blocks. Each memory block has a number of memory cells that can be selected through word and bit lines. In the customary one-transistor memory cell, a storage capacitor is connected to one of the bit lines through a selection transistor. A control connection of the selection transistor is connected to one of the word lines. The word and bit lines are disposed in the form of a matrix. The memory cells are configured at their points of intersection. Each memory block is delimited on two opposing sides by sense amplifiers. No more than one word line can be selected simultaneously per memory block because a plurality of memory cells would otherwise be connected to the same bit line simultaneously.
To repair faulty DRAMs, different redundancy methods are known in which word lines containing faulty memory cells are replaced by redundant word lines whose memory cells are intact. If appropriate redundancy programming is carried out, when a word address is applied that addresses the faulty word line, the redundant word line is selected instead of the faulty one, and selection of the faulty word line is prevented. The redundant word lines are configured parallel to the normal word lines in each memory block, and are connected to redundant memory cells. The redundant memory cells are similarly connected to the bit lines in the memory block.
A distinction is drawn between intrablock redundancy and interblock redundancy. With intrablock redundancy, only a redundant word line from the same memory block can replace a faulty word line. With interblock redundancy, a redundant word line from another memory block can also replace a faulty word line. While intrablock redundancy ensures that no more than one word line is ever activated within a block by replacing a faulty word line in a block with a redundant word line from the same block, it is possible that with interblock redundancy, in addition to an intact word line in a block being activated, a redundant word line in the same block (replacing a faulty word line in another block at the same instant) is also activated. To benefit from the advantages of interblock redundancy—namely, replacing word lines with redundant word lines from other blocks—the sacrifice must therefore be that only a single word line per group of memory blocks to which interblock redundancy applies is activated at the same instant, instead of one word line per memory block (as in the case of intrablock redundancy).
Because the storage capacitors used in dynamic memories lose their charge as a result of leakage currents, dynamic memories have an inherent property necessitating memory cell refreshing at certain intervals of time. Regular refreshing must be carried out for each memory cell. Because in memories with interblock redundancy not more than one word line is activated per interblock group, the same holds true for refreshing the memory cells. Therefore, refreshing takes a relatively long time.
German Published, Non-Prosecuted Patent Application 42 41 327 A1 describes a dynamic memory having memory cells combined to form blocks, and having bit lines and word lines for selecting the memory cells, the blocks being combined to form a block group.
IEEE Journal of Solid State Circuits, Volume 26, No. 11, Nov. 1, 1991, pages 1486-1491, Shigeru Mori et al., describes a dynamic memory having memory cells which are combined to form blocks and having bit lines and word lines for selecting the memory cells.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a dynamic memory having two modes of operation that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and that has improved properties.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a dynamic memory, including memory cells combined to form blocks and blocks combined to form block groups, bit lines and word lines connected to the memory cells for selecting the memory cells, redundant memory cells in the blocks, at least one redundant word line in at least one of the blocks, the at least one redundant word line connected to the redundant memory cells for selecting the redundant memory cells, the at least one redundant word line, after redundancy programming has been carried out, selectively replacing one of the word lines in any of the blocks, and a decoder unit connected to the word lines, in a first mode of operation, simultaneously selecting one of the word lines in each of the block groups, and in a second mode of operation, simultaneously selecting more than one of the word lines in each of the block groups and deactivating redundancy programming.
The dynamic memory according to the invention has memory cells that are combined to form blocks and are selected through bit lines and word lines. The blocks are combined to form at least one block group. The memory has a first mode of operation, in which only one of the word lines is selected simultaneously per block group, and a second mode of operation, in which more than one of the word lines are selected simultaneously per block group. A further provision of the invention is that the dynamic memory has interblock redundancy. Interblock redundancy means that at least one of its blocks has at least one redundant word line (containing redundant memory cells) that is used for selectively replacing one of the word lines in any of the blocks in the same block group after redundancy programming has been carried out. In addition, in the embodiment, redundancy programming that has already been carried out is deactivated in the second mode of operation.
Hence, in the second mode of operation, the deactivation unit is used to eliminate redundancy programming that has already been carried out, so that interblock redundancy is not active. Thus, one word line per block can be activated subsequently without any risk because no redundant word line can be active at the same time due to the deactivation of the redundancy.
In the second mode of operation, a larger number of word lines can advantageously be selected than in the first mode of operation in the same time. In the second mode of operation, one word line can be selected in each block at the same instant, for example.
The first mode of operation can, for example, be a normal mode of operation of the memory, in which the content of selected memory cells is read from the memory and new data is written into selected memory cells. The second mode of operation can, for example, be a refresh mode of operation, in which the content of at least some of the memory cells is refreshed. The memory cells are then advantageously refreshed in a shorter time than in the first mode of operation because a plurality of word lines per block group are refreshed simultaneously.
So that the redundant word lines can also be selected in the second mode of operation, one development of the invention provides for the redundant word lines to be assigned addresses that have already been precoded before redundancy programming is carried out and for the redundant word lines to be addressed using the precoded addresses or their complements in the second mode of operation (i.e., with redundancy programming deactivated). The configuration allows, by way of example, the redundant memory cells to be refreshed as well in the second mode of operation, in which redundancy programming is deactivated.
In one development of the invention, the dynamic memory has a test mode of operation for continuously testing the memory cells (burn-in test). During the test mode, the memory is switched to the second mode of operation. Thus, in the test mode, a larger number of word lines is selected than in the first mode of operation, so that the memory cells can advantageously be tested in a relatively short time. Particularly, if the second mode of operation is a refresh mode of operation, the burn-in test can be carried out in a relativ
Gratz Thoralf
Harle Dieter
Heyne Patrick
Schneider Helmut
Greenberg Laurence A.
Hoang Huan
Infineon - Technologies AG
Lerner Herbert L.
Stemer Werner H.
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