Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-02-19
2001-10-02
Pham, Long (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S758000, C438S130000, C438S278000
Reexamination Certificate
active
06297537
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to an improvement applicable to a semiconductor device and the like, such as a gate array, a mask ROM and the like, and to a method for production thereof. More specifically, this invention relates to an improvement applicable to multi-layer interconnections employable for a semiconductor device produced by supplementing one or more upper-layer interconnections to units selected out of those previously produced in a half-finished semiconductor device (a half-finished gate array, a half-finished mask ROM et al.) in which plural logic circuits and the wirings immediately connected thereto are produced and they are covered by an inter-layer insulator layer on which upper-layer interconnection is scheduled to be produced, and to an improvement applicable to a method for producing a multi-layer interconnection on the foregoing half-finished semiconductor device.
BACKGROUND OF THE INVENTION
Some type of semiconductor device or integrated circuit such as a gate array, a mask ROM and the like is produced by supplementing one or more upper-layer interconnections to units selected out of those previously produced in a half-finished semiconductor device (a half-finished gate array, a half-finished mask ROM et al.) in which plural logic circuits are produced and they are covered by an inter-layer insulator layer on which upper-layer interconnection is scheduled to be produced. In other words, a half-finished semiconductor device such as a half-finished gate array, a half-finished mask ROM and the like, on which plural logic circuits and the wirings immediately connected thereto have been produced but upper-layer interconnection to be connected thereto has not yet been produced is stocked, before final criteria are decided for the semiconductor device. After final criteria are decided, openings are produced to selected locations of an insulator layer which covers the wirings immediately connected to the logic circuits, the openings are buried by plug-shaped conductive pieces, and upper-layer interconnection having a horizontal shape decided following the final criteria, is produced to be connected with the plug-shaped conductive pieces. This production process has an advantage to decrease the process to be conducted after final criteria are decided and to shorten the production period to be conducted after final criteria are decided.
To meet a further requirement to further enhance the foregoing advantage, another system was developed. According to the improved system, process for production of plug-shaped conductive pieces is finished, before final criteria are decided and a process to produce upper-layer interconnection is applied only to selected plug-shaped conductive pieces, after final criteria are decided for the semiconductor device.
This improved system is involved with a drawback in which upper-layer interconnection is required to bypass the plug-shaped conductive pieces remained unselected. This is necessary to keep insulation between the upper-layer interconnection and the plug-shaped conductive pieces remained unselected which are connected monolithic electronic components e.g. transistors constituting the logic circuits produced on the semiconductor substrate.
OBJECTS AND SUMMARY OF THE INVENTION
Accordingly, the object of this invention is to provide a semiconductor device such as a gate array, a mask ROM and the like, produced by supplementing one or more upper-layer interconnections to units selected out of those previously produced in a half-finished semiconductor device (a half-finished gate array, a half-finished mask ROM et al.) in which plural logic circuits and the wirings immediately connected thereto are produced and they are covered by an inter-layer insulator layer on which upper-layer interconnection is scheduled to be produced, wherein the upper-layer interconnections are not requested to bypass the plug-shaped conductive pieces remained unselected.
The other object of this invention is to provide a method for producing the foregoing semiconductor device.
To achieve the foregoing object, a semiconductor device in accordance with a first embodiment of this invention comprising:
a semiconductor substrate on which a plurality of monolithic electronic components are produced,
an insulator layer covering the semiconductor substrate,
a plurality of contact pads arranged on the insulator layer and being connected the electrodes of the monolithic electronic components,
an inter-layer insulator layer covering the plurality of contact pads,
a plurality of plug-shaped conductive pieces penetrating the inter-layer insulator layer and being connected with the contact pad, and
at least one layer of upper-layer interconnections arranged above the inter-layer insulator layer and being connected with selected ones of the plug-shaped conductive pieces,
wherein the at least one layer of the upper -layer interconnections is connected with the selected ones of the plug-shaped conductive pieces through a connection pad, and the at least one layer of the upper -layer interconnections does not contact the top surface of the inter-layer insulator layer, remaining a space between the lower surface of the upper-layer interconnection and the top surface of the inter-layer insulator layer.
To achieve the foregoing object, a semiconductor device in accordance with a second embodiment of this invention comprising:
a semiconductor substrate on which a plurality of monolithic electronic components are produced,
an insulator layer covering the semiconductor substrate,
a plurality of contact pads arranged on the insulator layer and being connected the electrodes of the monolithic electronic components,
an inter-layer insulator layer covering the plurality of contact pads,
a plurality of plug-shaped conductive pieces penetrating the inter-layer insulator layer and being connected with the contact pad, and
at least one layer of upper-layer interconnections arranged above the inter-layer insulator layer and being connected with selected ones of the plug-shaped conductive pieces,
wherein the at least one layer of upper-layer interconnections is isolated from the unselected ones of the plug-shaped conductive pieces by an insulator layer arranged between the upper-layer and the interlayer insulator layer.
To achieve the foregoing other object, a method for producing a semiconductor device in accordance with a first embodiment of this invention comprising:
a step for producing a half-finished semiconductor device further comprising a semiconductor substrate on which plural monolithic electronic components are produced, an insulator layer covering the semiconductor substrate, a plurality of contact pads arranged on the insulator layer and being connected the electrodes of the monolithic electronic components, an inter-layer insulator layer covering the plurality of contact pads, and a plurality of plug-shaped conductive pieces penetrating the inter-layer insulator layer and being connected with the contact pad,
a step for producing a layer of a material which is conductive and accepts an etching process, produced on the inter-layer insulator and a conductive layer produced on the layer of a material which conductive and accepts an etching process, the foregoing two steps being conducted, before criteria are not yet decided for the semiconductor device,
a step for producing an etching mask of which the horizontal width is larger at locations corresponding to the selected ones of the plug-shaped conductive pieces than at locations corresponding to the unselected ones of the plug-shaped conductive pieces,
a step for etching the conductive layer and the layer of a material which is conductive and accepts an etching process by employing the etching mask, for producing an upper layer interconnection having a horizontal shape decided following criteria of the semiconductor device, out of the conductive layer and connection pads exclusively connected with the selected ones of the plug-shaped conductive pieces out of the layer of a material which is conductive and a
Coleman William David
Jones Volentine PLLC
OKI Electric Industry Co., Ltd.
Pham Long
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