Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2000-06-14
2001-02-20
Mai, Son (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S189050, C365S191000
Reexamination Certificate
active
06192005
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims priority from Korean Priority Document No. 99-22500, filed on Jun. 16, 1999 with the Korean Industrial Property Office, which document is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device. Particularly, the present invention relates to a clock control signal and output enable signal generator of semiconductor memory device in which a signal generating channel for controlling a low impedance of an output signal is different from that for controlling a high impedance, thereby improving an output enable signal generating speed, and at the same time supporting double cycle deselect, single cycle deselect and write pass through functions, both in a flow through operation and a pipe line read mode.
2. Description of the Prior Art
In a clock control signal and output enable signal generator of a conventional semiconductor memory device, an output enable signal shift is delayed. That is because a signal generating channel for controlling a low impedance in an output signal is identical to that for controlling a high impedance. Therefore, there has been a problem in that, when an output signal of the semiconductor memory device is shifted from a low impedance to a high impedance and from a high impedance to a low impedance, the shift speed is delayed.
This problem has been addressed by making the signal generating channel for controlling a low impedance different from the signal generating channel for controlling a high impedance. But a pipelined read operation of the semiconductor memory device includes single cycle deselect, double cycle deselect and write pass through functions. A problem is that all the single cycle deselect, double cycle deselect and write pass through functions cannot be supported (backed-up) with such different channels.
SUMMARY OF THE INVENTION
Accordingly, the present invention is provided to solve the aforementioned problem. It is an object of the present invention to provide a clock control signal and output enable signal generator in a semiconductor memory device, which can improve the speed in generating an output enable signal, while at the same time supporting all the single cycle, double cycle deselect and write pass through functions. The invention accomplishes this by making the signal generating channel for controlling a high impedance of an Output signal different from the signal generating chairmen for controlling a low impedance.
In accordance with the objects of the present invention, a clock control signal and output enable signal generator is made for a semiconductor memory device having a plurality of first registers for storing a plurality of data output signals, a plurality of second registers for storing the output signals of the first registers in response to a clock control signal, and a plurality of logic gates and output drivers for outputting the output signals of the plurality of the second registers in response to an output enable signal.
The generator of the invention comprises a first control signal and clock control signal generating means for generating a first control signal and a clock control signal, which are for controlling a shift of a high impedance to a low impedance after 1 cycle of a read command in a pipelined operation, and for generating a high level of clock control signal in a flow through operation. The invention also includes second control signal generating means for generating a low level of second control signal in a flow through operation, and generating the second control signal for controlling a shift from a low impedance to a high impedance ill a following cycle after read, deselect commands or read, write commands are sequentially input in a pipeline operation. It also includes a write pass through signal generating means for generating a write pass through signal in the read command cycle, in case write and read commands are sequentially input in a pipeline operation. Additionally, it includes a third control signal generating means for generating a third control signal for detecting a shift from a low impedance of low level to a high impedance of high level in an operation of double cycle deselect function, and for generating the third control signal in a deselect or write command cycle when read, deselect commands or read, write commands are sequentially input in an operation of single cycle deselect function. The invention moreover includes an output enable signal generating means for generating an output enable signal in response to an output enable control signal in a flow through operation, for generating the output enable signal of high level in response to the second control signal and a signal inverted from the first control signal, and for generating the output enable signal of low level in response to the third control signal or the second control signal in a pipeline operation.
REFERENCES:
patent: 5440514 (1995-08-01), Flannagan et al.
patent: 5920511 (1999-07-01), Lee et al.
patent: 5923595 (1999-07-01), Kim
patent: 5963483 (1999-10-01), Yahata et al.
patent: 6005825 (1999-12-01), Lee et al.
Mai Son
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
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