Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-03-29
2001-11-27
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S634000, C438S631000
Reexamination Certificate
active
06323125
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to a method whereby Plasma Polymerized Methylsilane (PPMS), a photosensitive polymer, forms an oxide layer, Plasma Polymerized Methylsilane Oxide (PPMSO), when exposed to UV light which forms the top insulating layer of a dual damascene insulating layer structure.
(2) Description of Prior Art
In the fabrication of semiconductor integrated circuits the dual damascene process is well known in the fabrication of multi-level conducting metal lines and interconnects.
Related patents teach various methods of photolithography processes to pattern metal lines both with and without dual damascene processing; but these methods do not cover the present invention which consists of using PPMS, a photosensitive polymer with dual damascene CMP processing.
U.S. Pat. No. 5,100,764 to Paulson et al teaches a method whereby sol gel, a colloidal suspension is used to form metal lines. A thin film of sol gel containing titanium, which is UV photo active, is exposed to UV activating the photo active compound which is then used to pattern the metal lines.
U.S. Pat. No. 5,487,967 to Hutton et al describes a photolithography process using a silylated resist that reacts with either exposed or unexposed regions of resist. The silylated resist is exposed to RIE and forms an “in situ” silicon dioxide etch mask, for precise image patterning from resist to substrate.
U.S. Pat. No. 5,591,676 to Hughes et al teaches a method of making a semiconductor device having a low permittivity dielectric. A fluorinated polymer layer is deposited on a metal, semiconductor or nonmetallic surface. The fluorinated polymer is heat treated and patterned by photolithography to form vias and then covered with a metal interconnect layer.
U.S. Pat. No. 5,689,140 to Shoda describes a method of forming studs and interconnects in multi-layered semiconductor devices. A dual damascene process is described with adhesion layers for each conductive layer.
U.S. Pat. No. 5,635,423 to Huang et al describes a dual damascene process to form multilevel metallization and inter-connect structures. An etch stop is described between the first and second insulating layers for via and trench patterning.
U.S. Pat. No. 5,705,849 to Zheng et al teaches a method for manufacturing an antifuse structure. A dual damascene process is described whereby structures comprising a pair of alternating layers of silicon nitride and amorphous silicon are sandwiched between two dual damascene connectors.
U.S. Pat. No. 5,041,361 to Tsuo describes an oxygen ion-beam lithographic patterning method using low-energy oxygen ion beams to oxidize amorphous silicon at selected regions. The non-oxidized regions are removed by etching in an RF excited hydrogen plasma.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide an improved method of forming integrated circuits in which a simplified dual damascene process uses CMP, chemical-mechanical polish to form planarized structures: metal line wiring, interconnects and via contacts, without the problem of dishing.
More specific to the invention is an improved method of forming planarized structures whereby Plasma Polymerized Methylsilane (PPMS), photosensitive polymer, forms an oxide layer, Plasma Polymerized Methylsilane Oxide (PPMSO), when exposed to UV illumination. The oxide layer PPMSO is patterned by a photomask to form the top layer of a dual damascene insulating layer structure. Conductive metal, copper, is deposited on to trench and via areas. CMP removes the excess metal and planarizes the surface since the PPMSO and copper can have similar CMP polishing rates. The process forms structures without dishing when PPMSO and copper are polished back at approximately the same rate.
Another object of the present invention is to provide planarized structures on semiconductor substrates to form: metal lines for wiring patterning, interconnects between multi-level metal layers, contacts through vias to metal lines and source/drain device contacts.
In accordance with the present invention, the above and other objectives are realized by using a method of fabricating a planarized structure on a semiconductor substrate, wherein a first insulating layer is provided. A second insulating layer over the first insulating layer is deposited. Patterning and etching of the second insulating layer follows to form an opening in the second insulating layer. A first layer of conducting metal is deposited on and into the second insulating layer. Then the excess conductive metal layer is polished back by CMP, chemical-mechanical polishing.
A third insulating layer is then deposited over the second insulating layer. Patterning and etching of the third insulating layer is performed to form openings on and over conducting metal lines, wiring pattern. Then, a layer of photosensitive polymer, Plasma Polymerized Methylsilane (PPMS) is deposited by Plasma Enhanced Chemical Vapor Deposition (PE CVD). PPMS is exposed to UV light using a photomask to form Plasma Polymerized Methylsilane Oxide (PPMSO); while blocking out the UV light in the trench and via openings. Unexposed PPMS is removed from the trench and via openings.
The said PPMS and PPMSO chemical formulas and reactions are outlined in the following section:
Methylsilane, Rf Plasma Deposition
PPMS, Plasma Polymerized Methylsilane
PPMS, Ultaviolet Exposure in Air
PPMSO, Plasma Polymerized Methylsilane Oxide
Next, a conductive barrier layer is conformally deposited and it provides a lining for the trench and via regions. This layer acts as diffusion barrier and CMP etch stop. A conductive metal layer is deposited and the excess metal is planarized by CMP without dishing when the CMP polishing rate of the conductive metal and the PPMSO, Plasma Polymerized Methylsilane Oxide, are similar.
In a second embodiment of the present invention, the above and other objectives are realized by using a simplified dual damascene technique to form a conductive contact to a semiconductor doped region, interconnection wiring pattern, via and conducting metal line, in the fabrication of an MOSFET device. Therefore, providing said active elements in said semiconductor substrate. A semiconductor substrate is provided with a first insulating layer, PE CVD TEOS (tetra-ethyl-ortho-silicate) deposited silicon oxide thereon. Patterning and etching of the silicon oxide is performed to form via holes for interconnects. At this point in the process, a layer of PPMS, photosensitive polymer is deposited by Plasma Enhanced CVD method, PE CVD. PPMS is exposed to UV light to form PPMSO, while a photomask blocks out the trench and via opening regions. The unexposed PPMS is removed from the trench and via openings. A barrier conducting layer, TaN (tantalum nitride), is deposited and lines both the trench and via. This layer of TaN acts as diffusion barrier and CMP etch stop. A thick conductive layer of Cu (Copper) is deposited and the excess metal is planarized by CMP without dishing. Key to this process is that the PMMSO and Cu CMP back at similar polishing rates.
REFERENCES:
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T. Weidman, D. Sugiarto, M. Nault, D. Mui, Z. Osborne, C. Lee, and J. Yang, “CVD Photoresist Processes for Sub-0. 18 Design Rules, ” 1998 Symposium on VLSI Technology Digest of Technical Papers, 9-11 Jun. 1998, pp. 166-
Chan Lap
Loh Wye Boon
Soo Choi Pheng
Bowers Charles
Chartered Semiconductor Manufacturing Ltd
Pike Rosemary L. S.
Saile George O.
Smoot Stephen W.
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