Reversible adiabatic logic circuit and pipelined reversible...

Details Reversible adiabatic logic circuit and pipelined reversible... Reversible adiabatic logic circuit and pipelined reversible...

2000-04-03

2001-11-13

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

C326S093000, C326S096000

Reexamination Certificate

active

06316962

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a reversible energy recovery logic circuit, and more particularly, to a reversible adiabatic logic circuit for eliminating non-adiabatic energy loss using a pair of PMOS transistors cross-coupled to an NMOS transistor network, and a pipelined reversible adiabatic logic apparatus employing the same.
2. Description of the Related Art
Adiabatic charging circuits have been steadily studied for attaining low-power consumption MOS logic circuits since they were proposed. In charging a voltage of a node in a standard CMOS logic circuit, assuming that a potential difference between both ends of switch is referred to as V
dd
, power of (½)C
L
V
dd
2
is consumed by switch resistance until the node (having capacitance C
L
) is completely charged when the switch (e.g., a MOSFET) connected to the power supply is turned off. However, if the voltage of the node becomes equal to the power supply voltage, even if the power supply is connected to the node by the switch, current does not flow into the switch, thereby avoiding power consumption due to the switch resistance.
Therefore, if the power supply voltage is increased relatively slowly, compared to a time constant RC
L
between the switch resistance R and the node capacitance C
L
, the node voltage can be increased to be substantially equal to the power supply voltage while reducing a potential difference between both ends of the switch. Then, the node voltage is conformed to the power supply voltage, thereby adiabatically charging the capacitance of the node. Here, the power dissipated by the switch resistance is represented as:
E=I
2
RT
=(
C
L
V
dd
/T
)
2
RT
=(2
RC
L
/T
)(½
C
L
V
dd
2
)  Equation (1)
wherein T denotes a time period for charging. Here, if T is infinitive, the power needed for charging the capacitance C
L
of the node can be made zero. This charging method is called an adiabatic charging method, which is markedly different from the standard charging method of a CMOS circuit free of the time constant RC
L
in context of dissipating energy.
In a CMOS inverter shown in
FIG. 1
, for example, if an input V
IN
applied to an input node N
1
changes in such a manner as shown in
FIG. 2A
, an output V
OUT
of an output node N
2
changes in such a manner as shown in FIG.
2
B. In other words, if the input V
IN
ramps down from a high level to a low level at a timing t
1
, a PMOS transistor Q
1
is turned on and an NMOS transistor Q
2
is turned off, so that the output node N
2
is charged up to the power supply voltage V
dd
by charging current I
1
, through the PMOS transistor Q
1
.
Conversely, if the input V
IN
ramps up from a low level to a high level at a timing t
2
, the PMOS transistor Q
1
is turned off and the NMOS transistor Q
2
is turned on, so that the output node N
2
is discharged to a power supply line
2
by discharging current
12
, through the NMOS transistor Q
2
.
Therefore, in the conventional charging method, as shown in
FIG. 3
, a potential difference V
1
between the constant power supply voltage V
dd
, i.e., &agr;1, and the voltage &agr;2 of the output node N
2
, may cause a switching loss. In this regard, according to the above adiabatic charging method, since the power supply voltage V
dd
changes as indicated by symbol &agr;3, and the voltage of the output node N
2
also changes as indicated by symbol &agr;4 in response to the change of the power supply voltage V
dd
, the loss caused thereby is reduced to a small amount corresponding to a potential difference indicated by symbol V
2
.
Recently, MOS transistor circuits using the above-described adiabatic charging method have been actively studied. For example, ECRL (Efficient Charge Recovery Logic) using the adiabatic charging method or dual-rail adiabatic logic circuit called a 2N-2N2P circuit has been proposed in publications by Y. Moon and D. K. Jeong, entitled “An Efficient Charge Recovery Logic Circuit,” IEEE Journal of Solid-State Circuits, Vol. 31, No. 4, 1996, pp. 514-522, and by A. Kramer, J. Denker and J. Moroney, entitled “2
nd
Order Adabatic Computation with 2N-2P and 2N-2N2P Logic Circuits,” International Symposium on Low Power Design, 1995, pp. 191-196.
However, these adiabatic logic circuits are associated with a non-adiabatic loss in addition to the adiabatic loss expressed in Equation (1). In the case of the 2N-2N2P circuits and ECRL circuits, the non-adiabatic loss is generated by a potential difference between both ends of a switch during a switching operation. In other words, in the 2N-2N2P circuits, an energy loss corresponding to C
L
V
dd
V
th
is generated by a diode used for precharging of the circuits. In the ECRL circuits, an energy loss corresponding to (½)C
L
V
th
2
is generated by threshold voltages (V
th
) of MOS transistors.
In order to avoid the non-adiabatic energy loss, the following two requirements must be satisfied. First, only when there is no potential difference between both ends of a switch (e.g., MOSFET), the switch must be turned on. When the switch is turned on in the presence of a potential difference between both ends thereof, an abrupt change in the voltage makes a large amount of current flow in the switch due to resistance present therein, thereby generating heat, which implies an energy loss. Second, once the switch is turned on, the energy must be slowly transferred so that a potential difference may not produced at both ends of the switch. The above-described adiabatic charging method has been proposed for satisfying these two requirements.
In order to supply the energy of a node and restore the same while satisfying the two requirements, it is necessary to know the state (or voltage) of the node, which can be solved by using reversible logic. The reversible logic is capable of reverse computation and allows the energy of an input stage to be restored by deriving an input value from an output value through a reverse logic function circuit. Therefore, the reversible logic can be used for restoration of energy.
One approach to low-power circuits using the reversible logic concept is reversible computer technology. Research into reversible computer systems aims at developing computers in which energy or power dissipation is very low. This is based on a physical theory asserting that no data loss leads to avoidance of energy loss, and those computers are promising next-generation computer models which can solve problems of heat and life. The important fields to which the reversible computer technology can be applied include a transplantation field of artificial internal organs, which requires extremely small power consumption. According to physical theories, computers can be designed so as not to consume energy if only reversible computation is allowed. Thus, reversible computers must be implemented using, reversible logic for reversible computation. However, most of conventional computation logic systems are irreversible. Thus, many approaches for converting the irreversible logic system into reversible ones have been disclosed. Existing Boolean functions which are mostly irreversible must be converted into reversible logic systems for being used, which may, however, cause an increase in the complexity. However, the complexity problem can be expected to overcome by the development of high-level integration technology. Ultimately, in view of minimization of energy dissipation, implementation of reversible logic circuits is a very important approach.
Logic elements and apparatuses for reducing energy dissipation using the above-described reversible logic and adiabatic charging method, have been disclosed in an article proposed by S. G. Younis and T. Knight, entitled “Asympotically Zero Energy Split-Level Charge Recovery Logic,” Workshop on Low Power Design, 1994, pp. 177-182, and an article proposed by W. C. Athas, L. Swensson, J. G. Koller, N. Tzartzanis and E. Y. -C. Chou, entitled “Low Power Digital Systems Based on Adiabatic Switching Principles,” IEEE Trans,

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