Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
1999-05-19
2001-02-20
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S106000, C438S107000, C438S108000, C438S110000, C438S111000, C438S112000, C438S123000, C257S678000, C257S685000, C257S686000, C257S692000, C257S693000, C257S723000, C257S730000
Reexamination Certificate
active
06190944
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor package and a fabrication thereof, and more particularly to a stacked package for a semiconductor device and a fabrication method thereof, and an apparatus for making the stacked package that increase the packaging density of a semiconductor chip without enlarging a system occupying area in a system device.
2. Description of the Conventional Art
Since the system device has been required to be miniaturized and light-weighted and have high efficiency, numerous studies have been vigorously made for a three-dimensional package, that is a stacked semiconductor package, in order to have more integrated circuits than the previous packages with the same size thereof. For the known stacked semiconductor package, there has been used a semiconductor package wherein thin small outline packages (TSOP) are stacked, the TSOP having the same planar size as the conventional package but half the thickness thereof.
FIG. 1
illustrates a structure of the conventional package T.
As shown therein, individual packages P, for example, four individual packages, are stacked, each package P having U-shaped outer leads
1
, and the outer leads
1
which are positioned along the same column are connected by one rail
2
. Thus, signal input and output between the outer leads
1
and a printed circuit board (not shown) are achieved through the rails
2
, the outer leads
1
being connected by being inserted into slots
4
formed at an inner edge of each rail
2
.
FIG. 2
is a cross-sectional view taken along the line of II—II of
FIG. 1
to show the connection between the rail
2
and the external leads
2
of the package.
As shown therein, the rail
2
is vertically formed and has the inner edge
3
facing a margin of a side of the individual package P. The inner edge
3
has the slots or recesses
4
which are formed in the same type of the external lead
1
. Further, an extension portion
5
is formed extendedly from a top portion of the rail
2
perpendicularly to the direction the rail
2
.
In other words, each external lead
1
of the individual semiconductor package P is inserted and thus fixed to the corresponding slot
4
of the rail
2
, and a lower surface
5
a
of the extension portion
5
is adhered by an adhesive to an upper surface Pa of the package P which is uppermost stacked. Accordingly, the multi-layered semiconductor packages P are not individually separated, but assembled into the stacked package T by the rails
2
and the extension portions
5
.
To fabricate such stacked semiconductor package T, first there is provided the individual semiconductor package P having the plurality of U-shaped outer leads
1
by the well-known fabrication method. More specifically, the method of fabricating the individual semiconductor package P includes die-attaching for attaching a semiconductor chip on a lead frame having inner and outer leads, wiring for connecting pads formed on the semiconductor chip to the inner leads thereof by wires, molding for covering the semiconductor chip, the wires and the inner leads by a molding compound and shaping for forming the shape of each outer lead to a U shape. Then, the individual semiconductor packages P are stacked and adhered by the adhesive.
Next, the external leads
1
of the individual semiconductor packages P are inserted into the corresponding slots
4
of the rails
2
and then the lower surfaces of the extension portions
5
extended from the top portions of the rails
2
are attached to the top surface of the uppermost stacked semiconductor package.
Further, solder dipping is processed by holding the individual semiconductor packages which are fixed as a single unit by the rails by a package binder and putting the rails and the outer leads into a solder paste box to dip the tips of the outer leads in the solder paste.
Finally, the rails and the outer leads are welded not to be separated from each other by reflowing for the solder covering the tips of the outer leads.
As described above, the rail takes charge of the signal input and output between external circuits of the printed circuit board and the semiconductor chip. However, as the number of the outer leads of the semiconductor package increases, the lead pitch decreases and accordingly rail-to-rail distance diminishes. Thus, in the solder dipping for fabricating the conventional stacked semiconductor package, the adjacent rails become short by the solder paste and the semiconductor device is not able to perform the normal signal input/output operation, which results in increase in the percent defective of the package.
Further, in the conventional package fabricating process, since the outer leads are manually inserted to the rails, the automation therefor can not be achieved. Thus, the package assembling process takes considerably long time and also the general package fabrication cost increase due to the increase in labor cost.
In addition, since the rails are required for fabricating the conventional package, except for the outer leads, compared to the previously developed stacked semiconductor packages, the fabrication cost of the package also unavoidably increase.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a stacked package for a semiconductor device and a fabrication method thereof, and apparatus for making the stacked package which obviate the problems and disadvantages due to the conventional art.
An object of the present invention is to provide a semiconductor package and a fabrication method thereof that fabricate a package having a narrow lead pitch due to a high-pin package system with relatively low fabrication costs, decrease percent defective of the package and increase the productivity thereof.
An object of the present invention is to provide a jig for package aligning used for fabricating a stacked package according to the present invention.
An object of the present invention is to provide a stacked semiconductor package by using a bottom leaded package (BLP).
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, there is provided a stacked semiconductor package including: a first-type package which consists of a semiconductor chip having a plurality of pads formed on a center portion of an upper surface thereof, leads of which end portions are attached on the upper surface of the semiconductor chip at outer sides of the pads and the other end portions are externally extended from the semiconductor chip, wires for connecting the ends portions of the leads to the corresponding pads, and a molding portion covering the semiconductor chip, the wires and portions of the leads; and a second-type package including a semiconductor chip having a plurality of pads formed on a center portion of a lower surface thereof, leads each of which consists of a chip-attached portion, a substrate-attached portion and a connecting portion and is formed in a ‘S’ shape, top surfaces of the chip-attached portions of the leads being respectively attached to portions of the lower surface of the semiconductor chip at the outer sides of the pads, wires for connecting end portions of the chip-attached portions to the corresponding pads, and a molding portion covering the semiconductor chip, the pads, the wires, and the chip-attached portions and the connecting portions of the leads; wherein the lower surfaces of the substrate-attached portions of the leads of the second-type package are welded by solder to upper surfaces of exposed portions of the leads of the first-type package which are externally extended out of the molding portion.
Further, in order to achieve the above objects of the present invention, there is provided a method for fabricating a stacked semiconductor package which includes the steps of: fabricating a first-type package including a semiconductor chip having a plurality of pads on a center portion of an upper surface thereof, leads of which end portions are attached on the uppe
Hyundai Electronics Industries Co,. Ltd.
Keshavan Belur
Smith Matthew
LandOfFree
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