Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
1999-12-10
2001-02-13
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S233100
Reexamination Certificate
active
06188620
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device having a redundancy judgment circuit and especially, to a semiconductor memory device having a redundancy judgment circuit that replaces a main memory cell with a redundancy memory cell at a high speed.
2. Description of the Prior Art
A redundancy judgment circuit is especially used for replacement of a defective cell in a memory such as a dynamic RAM.
In the prior art, when in replacement of a defective cell, in order to prevent a multi-word mode in which a main word line and a redundancy word line are simultaneously activated from occurring, activation of a main word line is delayed till it is definitely determined whether or not a redundancy word line is used, whereas in recent years, a high speed has been demanded in operation during which an address is supplied to a semiconductor memory device and subsequent to this, data stored in a memory cell is read out based on the address.
A circuit configuration according to a conventional technique is shown in
FIG. 7 and a
waveform timing chart of the circuit is shown in FIG.
8
.
First, address signals A
0
to Aj are externally supplied to address judgment circuits
10
to
13
. Herein, an address signal AjN is a complementary signal of a signal AjT. In the address judgment circuit
10
, the address signal inputs A
0
to Aj are compared with an address that is programmed with fuses in the address judgment circuit
10
and, when in coincidence, a judgment signal AC
0
retains a high level with no extraction of a charge (a solid line of AC
0
of FIG.
8
), while, when not in coincidence, the judgment signal AC
0
goes low with extraction of a charge (a broken line of AC
0
of FIG.
8
).
In the other address judgment circuits
11
to
13
as well, similar to the address judgment circuit
10
, comparisons regarding the addresses are conducted and comparative results are output as address judgment signals AC
1
to AC
3
.
Then, description will be made regarding operations of a redundancy judgment circuit
230
. The redundancy judgment circuit
230
is configured by: AND circuits
231
and
232
; latch circuits
233
and
234
; and a NOR circuit
235
.
In initial states, the latch circuits
233
and
234
output redundancy word control signals RDC
0
and RDC
1
at a low level. Therefore, the redundancy judgment circuit
230
in an initial state outputs a main word control signal XDC at a high level. That is, in the initial state, redundancy word drivers
40
and
41
are inactive, while a main word driver is active. Further, inverted signals of the judgment signals AC
0
and AC
1
are input to the AND circuit
231
, while inverted signals of the judgment signals AC
2
and AC
3
are input to the AND circuit
232
.
The latch circuits
233
and
234
receive outputs of the AND circuits
231
and
232
in response to a clock signal CLK
1
provided in a predetermined timing. The outputs of the latch circuits
233
and
234
show whether or not a redundancy word line is used. Further, the outputs of the latch circuits
233
and
234
are output to the NOR circuit
235
and a control signal XDC for a main word line is output from the NOR circuit
235
.
When the judgment signal AC
0
is high and the other signals AC
1
to AC
3
are low, an output of the AND circuit
231
goes low, while a control signal RDC
0
output from the latch circuit
233
goes high in response to the clock signal CLK
1
and is input to the redundancy word driver
40
. Further, the control signal RDC
0
is input to the NOR circuit
235
, and the control signal XDC changes from a high level to a low level and is input to the main word driver
50
(a solid line of XDC of FIG.
8
).
On the other hand, when the judgment signals AC
0
to AC
3
all are low, outputs of the AND circuits
231
and
232
go high. Hence, the control signals RDC
0
and RDC
1
are input to the redundancy word drivers
40
and
41
, while both remaining low. Further, the control signal XDC output from the NOR circuit
235
is input to the main word driver
50
, while remaining high (a broken line of XDC of FIG.
8
).
The redundancy word drivers
40
and
41
and the main word driver
50
are inactive or active when the control signals RDC
0
and RDC
1
, and the control signal XDC are low or high, wherein when a control signal goes high, and the corresponding word driver is activated and drives a word line.
Then, description will be made regarding to operations of address latch circuitry
30
. The address latch circuitry
30
is configured by latch circuits in the same number as the number of bits of an address and latches the address signals A
0
to Aj in response to a clock signal CLK
2
, is reset with a reset signal in initial state. Herein, the clock signal CLK
2
is produced by delaying the clock signal CLK
1
by a time &Dgr;t through a delay circuit
60
. The address latch circuitry
30
outputs the latched address, which is decoded by the address decoder
31
, to the main word driver
50
as selected address signal ASEL.
If, at this time, a judgment has not been made on whether a redundancy word line or a main word line is used, there arises a risk to activate both word lines together. That is, when the address latch circuitry
30
latches the address signals A
0
to Aj in response to the clock signal CLK
1
, the selected address signal ASEL is generated in a timing shown with a dashed line of ASEL of FIG.
8
. As described above, since an initial value of the control signal XDC is high, when the selected address signal ASEL is generated, there arises a risk that a main word line Main Word is driven by the main word driver
50
. Hence, the clock signal CLK
2
has been delayed from the clock signal CLK
1
sufficiently. When a main word line is used according to a judgment result, a total delay time is the sum of the delay time &Dgr;t and a delay time during which, in response to the clock signal CLK
2
, the address latch circuit
30
latches the address signals A
0
to Aj and outputs the selected address signal ASEL. Accordingly, the delay times become a fault to slow the operation of the memory device as whole.
In order to cope with this fault, a proposal has been made, for example, as disclosed in Japanese Patent Laid-Open No. 6-150686, in which controls of a redundancy word line and a main word line are absolutely separated. The method disclosed in this prior art reference is as shown in FIG.
9
.
That is, in address judgment circuits
130
to
133
, when an address signals A
0
to Aj input has no coincidence with a redundancy address programmed with fuses, all of judgment signals FUSE
0
to
3
go low and therefore, an AND circuit
140
outputs a control signal NEN at a high level. On the other hand, OR circuits
141
and
142
output control signals SPE
0
and SPE
1
at low levels.
Further, for example, when the address signals A
0
to Aj input coincide with a redundancy address in the address judgment circuit
130
, the judgment signal FUSE
0
goes low and the judgment signals FUSE
1
to FUSE
3
go high. Accordingly, the AND circuit
140
, OR circuit
141
and OR circuit
142
output judgment signals at a low level, a high level and a low level respectively.
However, this circuit has a configuration that cannot flexibly correspond to a change in address judgment circuits, especially increase in circuit scale thereof. That is, since controls of the redundancy word line and main word line are separated, when the number of the address judgment circuits (
130
to
133
) increases in order to deal with many of redundancy addresses, there arises a fault, since the AND circuit
140
for controlling a main word line is slowed in operation due to increase in number of input signals, which further delays the operation of a control signal NEN that serves as an enabling signal for a normal word line driver
153
. Furthermore, there arises another fault, since as the number of address judgment circuits increases, scales of control circuits for a redundancy word line and a main word lin
Le Vu A.
McGinn & Gibb PLLC
NEC Corporation
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