Electronic digital logic circuitry – Signal sensitivity or transmission integrity
Reexamination Certificate
1999-07-23
2001-02-06
Santamauro, Jon (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
C326S093000, C326S101000, C327S382000, C327S403000, C257S659000
Reexamination Certificate
active
06184702
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a circuit that reduces the influence of crosstalk in electronic circuits, and specifically, it relates to a crosstalk prevention circuit that reduces or removes the influence of crosstalk in digital signal processors (DSPs), ICs, or other types of semiconductor devices, etc.
BACKGROUND Of THE INVENTION
The explanation pertains to electronic circuits that are made up of semiconductor devices, for example, digital signal processors (DSPs), microprocessors, memory circuits, etc.
Various attempts have been made to miniaturize semiconductor devices and to increase their operating speed. However, an obstacle to changing to high-speed operation in these types of circuits is the signal propagation delays of the signal lines.
The signal propagation delay of signal lines is mainly due to the wiring resistance of the semiconductor device, for example, a metal film semiconductor device (MOS device), and the wiring capacitance (electrostatic wiring capacitance).
The main factor controlling the electrostatic wiring capacitance in manufacturing processes of up to about 0.8 &mgr;m is the electrostatic capacitances between the wires and the semiconductor substrate. However, accompanying progress in miniaturization, the distance between adjacent wires in the semiconductor device has been greatly reduced, the electrostatic capacitance between adjacent wires is impossible to ignore, and in manufacturing processes of 0.6 &mgr;m and below, when the wiring is formed with minimum spacing, the electrostatic capacitance between adjacent wires accounts for more than 90% of the total electrostatic capacitance.
Crosstalk has increased due to the increase in electrostatic capacitance between wires. The increase in crosstalk increases the signal delay. Such signal delays that result from crosstalk are the cause of various problems.
For example, when crosstalk occurs in the clock wiring, there are instances when deterioration of performance occurs that results from the delay of the clock, and there is the possibility that with a two phase clock, skewing (phase offset) between the two phase clocks occurs.
Also, if crosstalk occurs in a bus line, the delay due to the crosstalk will limit the operating speed of the IC. That is, the crosstalk will determine the operating speed of the IC.
In other electronic circuits problems also occur, such as skewing, lowering the operating speed, and operating errors due to distortion of the pulse signal, which originate with crosstalk in the same manner.
In general, there have been various attempts to prevent this type of crosstalk. For example, in one method the distance between adjacent wires is increased, but this method cannot be applied to semiconductor devices and semiconductor circuits in which miniaturization has advanced since the surface area increases.
As another general method, there is the method that adopts barriers (shields). However, if shields are implemented, the surface area becomes a problem. The fact that new area is required for implementation of shields makes this method inapplicable to the semiconductor devices and Ics whose fineness and integration level are required to be further improved.
Therefore, the present invention offers a circuit wherein the crosstalk can be reduced or eliminated with a method that does not affect improvements in miniaturization or the integration level.
SUMMARY OF INVENTION
According to the first point of view of the present invention, a crosstalk prevention circuit is offered wherein between at least two approximately parallel signal lines, a third signal line is installed, to which a signal is applied when a signal that is to be applied to at least one of aforementioned two signal lines is not present and which becomes grounded when a signal is applied to the above-mentioned two signal lines.
Preferably, a driver circuit is connected to the above-mentioned third single line, and the ratio of the current drive capabilities of the N-channel transistor and the P-channel transistor of the output transistors of said driver circuit is about 2:1.
Also, preferably, a first clock and a second clock that has a prescribed phase difference relative to said first clock are applied to the above-mentioned first and second signal lines, and a signal that is applied during test operations is applied to the above-mentioned third signal line.
Also, preferably, the above-mentioned first and second signal lines are signal lines in which the voltage is changed by means of a first signal, and the above-mentioned third signal line is a signal line in which the voltage is changed by means of a signal having a phase that is different than the above-mentioned first signal.
Also, according to the second point of view of the present invention, a crosstalk prevention circuit is offered having wiring that is characterized in that the first power supply metal wiring and the second power supply metal wiring are provided in parallel separated by a prescribed distance at both sides of the metal signal wiring on which a pulse signal is propagated, and the width of the above-mentioned metal signal wiring and the above-mentioned first and second power supply metal wiring are made widths in which the resistance to electromigration is improved.
Preferably, even if the above-mentioned metal signal wiring, the above-mentioned first power supply metal wiring, and the above-mentioned second metal wiring are in different layers, the above-mentioned metal signal wiring is surrounded by the above-mentioned first power supply metal wiring and the above-mentioned second power supply metal wiring.
REFERENCES:
patent: 5136358 (1992-08-01), Sakai et al.
patent: 5306967 (1994-04-01), Dow
patent: 5646556 (1997-07-01), Longwell et al.
patent: 5994946 (1999-11-01), Zhang
patent: 6081022 (2000-01-01), Mitra et al.
Ozawa Kayoko
Takahashi Hiroshi
Tashiro Kenichi
Kempler William B.
Santamauro Jon
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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