Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-09-03
2001-02-13
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
Reexamination Certificate
active
06188106
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to a transistor having formed in the active area a highly doped liner layer to decrease channel capacitance and prevent punchthrough and a barrier layer to prevent diffusion of the liner layer into the channel and the junction areas.
2. Description of the Related Art
Fabrication of a MOSFET device is well known. Generally speaking, MOSFETs are manufactured by placing undoped polycrystalline silicon (“polysilicon”) over a relatively thin gate oxide. The polysilicon material is then patterned to form a gate conductor directly above a channel region of the substrate. A dopant species is implanted into the gate conductor and regions of the substrate exclusive of the channel region, thereby forming source and drain regions adjacent to and on opposite sides of the channel region. If the dopant species used for forming the source and drain regions is n-type, then the resulting MOSFET is an NMOSFET (“n-channel”) transistor device. Conversely, if the dopant species is p-type, then the resulting MOSFET is a PMOSFET (“p-channel”) transistor device. Integrated circuits may utilize either n-channel devices exclusively, p-channel devices exclusively, or a combination of both on a single substrate. While both types of devices may be formed, the devices are distinguishable based on the dopant species used.
Because of the increased desire to build faster and more complex integrated circuits, it has become necessary to reduce the transistor threshold voltage, V
T
. Several factors contribute to V
T
, one of which is the effective channel length (“L
eff
”) of the transistor. The initial distance between the source-side junction and the drain-side junction of a transistor is often referred to as the physical channel length, L. However, after implantation and subsequent diffusion of the junctions, the electrical distance between junctions becomes less than the physical channel length and is often referred to as the effective channel length, L
eff
. In VLSI designs, as the physical channel length decreases, so too must L
eff
. Decreasing L
eff
reduces the distance between the depletion regions associated with the source and drain of a transistor. As a result, less gate charge is required to invert the channel of a transistor having a short L
eff
Accordingly, reducing L, and hence L
eff
, may lead to a reduction in the threshold voltage of a transistor. Consequently, the switching speed of the logic gates of an integrated circuit employing transistors with reduced L
eff
is faster, allowing the integrated circuit to quickly transition between logic states (i.e., operate at high frequencies). Minimizing L also improves the speed of integrated circuits including a large number of individual transistors because the larger drain current associated with a short channel length can drive the adjoining transistors into saturation more quickly. Also, the smaller L has less parasitic capacitance. Minimizing L is, therefore, desirable from a device operation standpoint.
In addition, minimizing L is desirable from a manufacturing perspective because a smaller area of silicon is required to manufacture a transistor having a smaller length. By minimizing the area required for a given transistor, the number of transistors available for a given area of silicon increases, with a corresponding increase in the circuit complexity that can be achieved on the given area of silicon. As layout densities increase, however, the problems associated with fabrication of transistors are exacerbated. Although n-channel devices are particularly sensitive to so-called short-channel effects (“SCE”), SCE also becomes a predominant problem in p-channel devices whenever L
eff
drops below approximately 0.8 &mgr;m.
While in operation, transistors that have heavily doped source and drain regions arranged laterally adjacent the gate conductor often experience a problem known as punchthrough, which can lead to an undesirable increase in the subthreshold current, I
Dst
. Punchthrough occurs when the reverse-bias voltage on the drain is increased, leading to a widening of the drain depletion region. The drain may eventually merge into the source region, thereby reducing the potential energy barrier of the source-to-body junction. As a result, more majority carriers in the source region will have sufficient energy to overcome the barrier, causing an increased source-to-body current flow. Collection of some of this current by the drain leads to an increase in I
DSt
.
To prevent short-channel MOSFETS from entering punchthrough, the substrate doping may be increased to increase the depletion-layer widths. For many long-channel devices, a single implant may serve as both a punchthrough stop and a V
T
adjust. In cases where a single implant is inadequate, such as in submicron MOSFETs, a second, deeper implant may be provided. The punchthrough stopper may be implanted such that its peak concentration is located at a depth near the bottom of the source and drain regions. This additional doping advantageously reduces the lateral widening of the drain depletion region below the substrate surface. Formation of a punchthrough stopper, however, requires close control of the implant placement and dose within the channel region. In addition, it is important that the punchthrough implant be kept from spreading during subsequent annealing of the substrate.
It would therefore be desirable to fabricate a submicron transistor having a punchthrough implant that is prevented from encroaching upon the channel and junction regions of the active area during subsequent thermal processing of the semiconductor substrate.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by the technique hereof for forming a transistor having increased resistance to punchthrough and decreased channel capacitance. In one embodiment, isolation structures are formed within isolation regions of a semiconductor substrate. The isolation regions preferably include silicon dioxide and may be formed using, for example, the well-known trench isolation method or local oxidation of silicon (“LOCOS”).
Following formation of the isolation structures, a liner layer may be formed in the active region of the semiconductor substrate by implanting a high concentration of dopant ions into the substrate. Preferably, the implant energy is sufficient to implant the liner layer to a depth below a depth at which lightly doped drain and source/drain impurity areas may subsequently be formed. Preferably, the liner implant is of a conductivity type opposite the conductivity type of the device to be formed. For example, in an NMOS embodiment, the liner implant ions may include p-type species, and in a PMOS embodiment, the liner implant ions may include n-type species.
Using an NMOS device as an example, boron ions may be implanted into the semiconductor substrate at an energy between about 100 keV and about 500 keV and a concentration between about 5×10
14
cm
−2
and about 8×10
15
cm
−2
. By way of comparison, conventionally formed punchthrough stop implants may be performed at a concentration of about 10
11
to 10
12
cm
−2
. The resulting liner layer is preferably formed at a depth of between about 300 angstroms and about 2000 angstroms beneath the surface of the semiconductor substrate. Alternatively, other sources for p-type ions, such as boron difluoride, may be used to form the liner layer.
Following formation of the liner layer, a sacrificial layer may be formed upon the upper surface of the semiconductor substrate. Preferably, the semiconductor substrate includes single crystal silicon and the sacrificial layer includes silicon dioxide thermally grown upon the upper surface of the semiconductor substrate to a thickness of between about 100 angstroms and about 300 angstroms.
A barrier layer may then be formed by implanting barrier ions into the semiconductor substrate at a depth less than the depth of the liner l
Fulford Jr. H. Jim
Gardner Mark I.
May Charles E.
Advanced Micro Devices , Inc.
Conley Rose & Tayon
Daffer Kevin L.
Meier Stephen D.
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