Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
1998-10-07
2001-02-06
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S039000, C326S040000, C326S041000, C326S038000
Reexamination Certificate
active
06184707
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the field of programmable logic integrated circuits. More specifically, the present invention provides an enhanced programmable logic architecture, improving upon the composition, configuration, and arrangements of logic array blocks (LABs) and logic elements (LEs) and also the interconnections between these logic array blocks and logic elements.
Programmable Logic Devices (PLDs) are well known to those in the electronic art. Such programmable logic devices are commonly referred as PALs (Programmable Array Logic), PLAs (Programmable Logic Arrays), FPLAs (Field Programmable Logic Arrays), PLDs (Programmable Logic Devices), EPLDs (Erasable Programmable Logic Devices), EEPLDs (Electrically Erasable Programmable Logic Devices), LCAs (Logic Cell Arrays), FPGAs (Field Programmable Gate Arrays), and the like. Such devices are used in a wide array of applications where it is desirable to program standard, off-the-shelf devices for a specific application. Such devices include, for example, the well-known, Classic™, and MAX® 5000, and FLEX® 8000 EPLDs made by Altera Corp.
PLDs are generally known in which many LABs are provided in a two-dimensional array. Further, PLDs have an array of intersecting signal conductors for programmably selecting and conducting logic signals to, from, and between the LABs. LABs contain a number of individual programmable logic elements (LEs) which provide relatively elementary logic functions such as NAND, NOR, and exclusive OR.
Resulting from the continued scaling and shrinking of semiconductor device geometries which are used to form integrated circuits (also known as “chips” ), integrated circuits have progressively become smaller and denser. For programmable logic, it becomes possible to put greater numbers of programmable logic elements onto one integrated circuit. Furthermore, as the number of elements increases, it becomes increasingly important to improve the techniques and architectures used for interconnecting the elements and routing signals between the logic blocks.
While such devices have met with substantial success, such devices also meet with certain limitations, especially in situations in which the provision of more complex logic modules and additional or alternative types of interconnections between the logic modules would have benefits sufficient to justify the additional circuitry and programming complexity. There is also a continuing demand for logic devices with larger capacity. This produces a need to implement logic functions more efficiently and to make better use of the portion of the device which is devoted to interconnecting individual logic modules.
As can be seen, an improved programmable logic device architecture is needed, especially a programmable logic element which improves the organization of logic modules and interconnection resources within the logic element.
SUMMARY OF THE INVENTION
The present invention is a programmable logic element which facilitates the implementation of logical functions in a programmable logic device. The present invention includes a programmable, multi-input look-up table which can generate desired logical functions. The present invention further includes a storage block which can store data from the look-up table. Furthermore, the storage block is configurable to operate as a level-sensitive latch or an edge-triggered register. The storage block includes clock, clock enable, clear, and preset inputs for controlling these functions of the storage block. One or more of the inputs to the look-up table and optionally, their complements may be programmably selected to control the clock, clock enable, clear, and preset inputs. The logic element is configurable for either combinatorial or registered output.
The logic element may be coupled to a secondary logic block providing specialized logic functions. The secondary logic block may selectively take input from one or more of the four inputs to the look-up table (or their complements), as well as the output of the look-up table. Output from the secondary logic block is selectively passed through the registered output path of the logic element. The logic element also includes a diagnostic shadow latch used for prototyping and debugging new programmable logic designs.
More specifically, in accordance with the teachings of this invention, a logic element for a programmable logic device is disclosed, which includes a look-up table for implementing logical functions; a storage block coupled to the look-up table, where the storage block stores an output from the look-up table and is programmably configurable as a latch in a first mode, where the latch is responsive to a level-sensitive clock input, and where the storage block is programmably configurable as a register in a second mode, where the register is responsive to an edge-triggered clock input. The register may be further responsive to a clock enable input. Furthermore, the logic element has a combinatorial output, coupled to the look-up table, and a registered output, coupled to the storage block.
In further embodiments of the present invention, the logic element includes a programmable delay block, coupled between the look-up table and the storage block, where this programmable delay block is for programmably delaying a signal passed from the look-up table to the storage block.
In another embodiment, the logic element includes a first plurality of input lines, coupled to the look-up table and the storage block, where this first plurality of input lines is for conducting a plurality of logic signals, and a second plurality of input lines, coupled to the storage block, where this second plurality of input lines is for conducting complements of the plurality of logic signals.
Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings, in which like reference designations represent like features throughout the figures.
REFERENCES:
patent: Re. 34363 (1993-08-01), Freeman
patent: 3473160 (1969-10-01), Wahlstrom
patent: 3761695 (1973-09-01), Eichelberger
patent: 3783254 (1974-01-01), Eichelberger
patent: 3806891 (1974-04-01), Eichelberger et al.
patent: 4020469 (1977-04-01), Manning
patent: 4124899 (1978-11-01), Birkner et al.
patent: 4286173 (1981-08-01), Oka et al.
patent: 4293919 (1981-10-01), Dasgupta et al.
patent: 4298980 (1981-11-01), Hajdu et al.
patent: 4336393 (1982-06-01), Sih
patent: 4428060 (1984-01-01), Blum
patent: 4476560 (1984-10-01), Miller et al.
patent: 4488259 (1984-12-01), Mercy
patent: 4546273 (1985-10-01), Osman
patent: 4597042 (1986-06-01), d'Angeac et al.
patent: 4609986 (1986-09-01), Hartmann et al.
patent: 4617479 (1986-10-01), Hartmann et al.
patent: 4642487 (1987-02-01), Carter
patent: 4649539 (1987-03-01), Crain et al.
patent: 4667325 (1987-05-01), Kitano et al.
patent: 4677318 (1987-06-01), Veenstra
patent: 4701920 (1987-10-01), Resnick et al.
patent: 4706216 (1987-11-01), Carter
patent: 4713792 (1987-12-01), Hartmann et al.
patent: 4717912 (1988-01-01), Harvey et al.
patent: 4871930 (1989-10-01), Wong et al.
patent: 4899067 (1990-02-01), So et al.
patent: 4912342 (1990-03-01), Wong et al.
patent: 5036473 (1991-07-01), Butts et al.
patent: 5109353 (1992-04-01), Sample et al.
patent: 5121006 (1992-06-01), Pedersen
patent: 5241224 (1993-08-01), Pedersen et al.
patent: 5260610 (1993-11-01), Pedersen et al.
patent: 5260611 (1993-11-01), Cliff et al.
patent: 5317212 (1994-05-01), Wahlstrom
patent: 5329470 (1994-07-01), Sample et al.
patent: 5336950 (1994-08-01), Popli et al.
patent: 5350954 (1994-09-01), Patel
patent: 5352123 (1994-10-01), Sample et al.
patent: 5355369 (1994-10-01), Greenbergerl et al.
patent: 5375086 (1994-12-01), Wahlstrom
patent: 5392296 (1995-02-01), Suzuki
patent: 5414377 (1995-05-01), Freidin
patent: 5436575 (1995-07-01), Pedersen et al.
patent: 5452239 (1995-09-01), Dai et al.
patent: 5477475 (1995-12-01), Sample et al.
patent: 5488316 (1996-01-01), Freeman et al.
patent: 55
Butts Michael R.
Norman Kevin A.
Patel Rakesh H.
Sample Stephen P.
Altera Corporation
Tan Vibol
Tokar Michael
Townsend and Townsend / and Crew LLP
LandOfFree
Look-up table based logic element with complete... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Look-up table based logic element with complete..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Look-up table based logic element with complete... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2604512