Capacitors, methods of forming capacitors, and DRAM memory...

Details Capacitors, methods of forming capacitors, and DRAM memory... Capacitors, methods of forming capacitors, and DRAM memory...

1998-02-28

2001-02-20

Wojciehowicz, Edward (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S301000, C257S303000, C257S532000, C257S640000

Reexamination Certificate

active

06191443

ABSTRACT:

TECHNICAL FIELD
This invention relates to capacitors, to methods of forming capacitors, and to DRAM cells.
BACKGROUND OF THE INVENTION
As DRAMs increase in memory cell density, there is a continuing challenge to maintain sufficiently high storage capacitance despite decreasing cell area. Additionally, there is a continuing goal to further decrease cell area. One principal way of increasing cell capacitance is through cell structure techniques. Such techniques include three-dimensional cell capacitors, such as trenched or stacked capacitors. Yet as feature size continues to become smaller and smaller, development of improved materials for cell dielectrics as well as the cell structure are important. The feature size of 256 Mb DRAMs will be on the order of 0.25 micron, and conventional dielectrics such as SiO
2
and Si
3
N
4
might not be suitable because of small dielectric constants.
Highly integrated memory devices, such as 256 Mbit DRAMs, are expected to require a very thin dielectric film for the 3-dimensional capacitor of cylindrically stacked or trench structures. To meet this requirement, the capacitor dielectric film thickness will be below 2.5 nm of SiO
2
equivalent thickness. Chemical vapor deposited (CVD) Ta
2
O
5
films are considered to be very promising cell dielectric layers for this purpose, as the dielectric constant of Ta
2
O
5
is approximately three times that of conventional Si
3
N
4
capacitor dielectric layers. However, one drawback associated with Ta
2
O
5
dielectric layers is undesired leakage current characteristics. Accordingly, although Ta
2
O
5
material has inherently higher dielectric properties, as-deposited Ta
2
O
5
typically produces unacceptable results due to leakage current.
Densification of Ta
2
O
5
as deposited has been reported to significantly improve the leakage characteristics of such layers to acceptable levels. Prior art densification of such layers includes exposing the Ta
2
O
5
layer to extreme annealing and oxidizing conditions. The anneal drives any carbon present out of the layer and advantageously injects additional oxygen into the layer such that the layer uniformly approaches a stoichiometry of five oxygen atoms for every two tantalum atoms. The oxygen anneal is commonly conducted at a temperature of from about 400° C. to about 1000° C. utilizing an ambient comprising an oxygen containing gas. The oxygen containing gas commonly comprises one or more of O
3
, NO, N
2
O and O
2
. The oxygen containing gas is typically flowed through a reactor at a rate of from about 0.5 slm to about 10 slm.
The Ta
2
O
5
layer is typically from about 40 angstroms to about 150 angstroms thick and can be either amorphous or crystalline. Ta
2
O
5
is generally amorphous if formed below 600° C. and will be crystalline if formed, or later processed, at or above 600° C. Typically, a Ta
2
O
5
layer is deposited as an amorphous layer and the above-described oxygen anneal is conducted at a temperature of 600° C. or greater to convert the amorphous Ta
2
O
5
layer to a crystalline layer. Undesirably, however, such has a tendency to form an SiO
2
layer intermediate or between the polysilicon and Ta
2
O
5
. Further and regardless, a thin SiO
2
layer will also typically inherently form during the Ta
2
O
5
deposition due to the presence of oxygen at the polysilicon layer interface. It would be desirable to remove or eliminate this SiO
2
layer intermediate the Ta
2
O
5
and polysilicon layers, yet allow for such desired densification.
One prior art technique reported includes exposing the polysilicon layer to rapid thermal nitridation prior to subsequent deposition of the Ta
2
O
5
layer. Such are reported by Kamiyama et al., “Ultrathin Tantalum Oxide Capacitor Dielectric Layers Fabricated Using Rapid Thermal Nitridation prior to Low Pressure Chemical Vapor Deposition”, J. Electrochem. Soc., Vol. 140, No. 6, June 1993 and Kamiyama et al., “Highly Reliable 2.5 nm Ta
2
O
5
Capacitor Process Technology for 256 Mbit DRAMs”, 830-IEDM 91, pp. 32.2.1-32.2.4. Such rapid thermal nitridation includes exposing the subject polysilicon layer to temperatures of from 800° C. to 1100° C. for sixty seconds in an ammonia atmosphere at atmospheric pressure. The nitride layer acts as a barrier layer to oxidation during Ta
2
O
5
deposition and subsequent high temperature densification processes to prevent oxidation of the underlying polysilicon electrode. These processes do however have several drawbacks, including the undesired high temperature cycling and formation of a fairly thick native SiO
2
on the nitride in series with the Ta
2
O
5
, all of which adversely effects the realization of high capacitance promised by inherent Ta
2
O
5
layers.
SUMMARY OF THE INVENTION
The invention comprises capacitors, methods of forming capacitors and DRAM circuitry. In one implementation, a capacitor comprises a capacitor dielectric layer comprising Ta
2
O
5
formed over a first capacitor electrode. A second capacitor electrode is formed over the Ta
2
O
5
capacitor dielectric layer. Preferably, at least a portion of the second capacitor electrode is formed over and in contact with the Ta
2
O
5
in an oxygen containing environment at a temperature of at least about 175° C. Chemical vapor deposition is one example forming method. The preferred second capacitor electrode comprises a conductive metal oxide. A more preferred second capacitor electrode comprises a conductive silicon comprising layer, over a conductive titanium comprising layer, over a conductive metal oxide layer. A preferred first capacitor electrode comprises a conductively doped Si-Ge alloy. Preferably, a Si
3
N
4
layer is formed over the first capacitor electrode.


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