Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2000-02-16
2001-11-20
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S508000, C257S390000, C257S672000, C257S637000
Reexamination Certificate
active
06320240
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device in which contact plugs for connecting by a self-alignment fashion electrically between impurity diffusion regions formed on a semiconductor substrate and overlying wirings and a method of manufacturing the same.
2. Description of the Prior Art
In recent years, the high integration of LSI (Large Scale Integrated Circuit) is advanced much more, and it is requested to form finely much more respective elements. However, with the progress of miniaturization of the device, it becomes difficult to form the contact plugs which connect electrically the impurity diffusion regions formed on the semiconductor substrate and the wirings.
Normally the contact plugs are formed by using the photolithography technology. More particularly, photoresist is coated on the insulating film formed on the semiconductor substrate, and then the photoresist is exposed via a reticle (exposure mask) having a desired hole pattern. Then, the opening portions are formed in the photoresist by applying the developing process, and then the contact holes are formed in the insulating film by etching the insulating film while using the photoresist as an etching mask. Then, the contact plugs are formed by burying the contact holes by the conductive material.
The contact holes must also be miniaturized according to the miniaturization of the devices. If the hole patterns of the reticle are reduced in size to miniaturize the contact holes, an enough amount of light cannot be irradiated onto the resist in exposure and thus sometimes the holes are not opened. In order to avoid this event, if the hole patterns of the reticle is tried to increase in size so as to increase an exposure amount of light, the neighboring holes are connected mutually.
Therefore, in order to form the fine contact plugs smaller than the resolution of the photolithography, the technologies for manufacturing the contact plugs in a self-alignment fashion have been proposed (Y.Kohyama et al., Sympo. on VLSI Technology Digest, p.17, 1997, K. N. Kim et al. Sympo. on VLSI Technology Digest, p.16, 1998).
FIGS. 1
to
3
are views showing a method of manufacturing a semiconductor device (DRAM: Dynamic Random Access Memory), in which the contact plugs are formed in a self-alignment fashion, in the prior art in the order of step.
As shown in a tip view of FIG.
1
A and as shown in a sectional view of
FIG. 1B
taken along a
1
B—
1
B line in
FIG. 1A
, the device isolation regions are formed by the buried device isolation (Shallow Trench Isolation: referred simply to as “STI” hereinafter) method. More particularly, the trenches are etched on the semiconductor substrate
51
, and then the device isolation regions
52
are formed by burying the trenches by the silicon oxide. The semiconductor substrate
51
is partitioned into a plurality of device regions
53
by the device isolation regions
52
. In this example, as shown in
FIG. 1A
, the device regions
53
are formed like an oval rectangular and arranged like a mosaic pattern. Then, the gate oxide film (not shown) is formed by thermally oxidizing the surface of the device regions
53
on the semiconductor substrate
51
.
Then, the polysilicon film, the tungsten silicide film, and the silicon nitride film are formed sequentially on the overall upper surface of the semiconductor substrate
51
. Then, as shown in a top view of FIG.
1
C and as shown in a sectional view of
FIG. 1D
, a plurality of word lines
54
which are arranged in parallel mutually are formed. As shown in
FIG. 1D
, for example, each of the word lines
54
consists of the polysilicon film
56
a
and the tungsten silicide film
56
b
. Then, the impurity is introduced into both side portions of the word lines
54
in the device regions
53
.
Then, a silicon nitride film is formed on the overall upper surface of the semiconductor substrate
51
. Then, the silicon nitride film is left only on both sides of the word lines
54
by anisotropically etching the silicon nitride film to thus form sidewall spacers. A protection film
57
in
FIG. 1D
consists of the sidewall spacers and the silicon nitride film being formed previously on the word lines
54
.
Then, as shown in a top view of FIG.
1
E and as shown in a sectional view of
FIG. 1F
taken along an
1
F—
1
F line in
FIG. 1E
, a BPSG (Boron-doped Phospho-Silicate Glass) film is formed on the semiconductor substrate
51
, and also plug insulating films
61
which have the same shape (oval rectangular) as the device regions
53
respectively are formed at positions adjacent to the device regions
53
by patterning the BPSG film.
Then, as shown in a top view of
FIG. 2
, as shown in a sectional view of
FIG. 3A
taken along an
3
A—
3
A line in
FIG. 2
, and as shown in a sectional view of
FIG. 3B
taken along a
3
B—
3
B line in
FIG. 2
, the overall upper surface of the semiconductor substrate
51
is covered with conductive polysilicon, and then the polysilicon is polished by the CMP (Chemical Mechanical Polishing) method until the plug insulating films
61
and the protection film
57
are exposed. Hence, the contact plugs
59
(cross-hatched portions in
FIG. 2
) are formed by the remaining conductive polysilicon. In turn, contact windows used to form contact between the interlayer insulating film and the contact plugs
59
, wirings (bit lines), capacitors, and metal wirings are formed over the semiconductor substrate
51
, so that the semiconductor device can be completed.
According to this method, since a size and a position of the contact plug
59
are decided by positions of the word lines
54
and the plug insulating films
61
, fine contact plugs can be formed at a high density without the influence of the resolution at the time of exposure.
Normally, it is known that the device isolation regions formed by the LOCOS (Local Oxidation of Silicon) method are protruded from the surface of the substrate. In this case, even if the device isolation regions are formed by the above-mentioned STI method, the device isolation regions are formed to be protruded slightly from the surface of the substrate.
A method of forming the device isolation regions by the STI method and problems caused in the prior art will be explained in detail with reference to
FIGS. 4
to
6
hereinafter. Where same reference numerals are affixed in
FIGS. 4
to
6
to the same constituent elements as those shown in
FIGS. 1
to
3
, and their redundant explanation will be omitted hereunder.
To begin with, as shown in
FIG. 4A
, a silicon nitride film is formed as a stopper film
71
on the semiconductor substrate
51
, and then trenches (recesses)
52
a
are formed on regions acting as the device isolation regions
52
. Then, silicon oxide is deposited on the overall upper surface of the semiconductor substrate
51
to bury the trenches
52
a
and to form a silicon oxide film
72
on the substrate
51
.
Then, as shown in
FIG. 4B
, the stopper film
71
is exposed by polishing the silicon oxide film
72
on the semiconductor substrate
51
by virtue of the CMP method. In this manner, the device isolation regions
52
can be formed.
When the silicon oxide film
72
on the semiconductor substrate
51
is polished by the CMP method, the polishing is quickly proceeded in a portion where the device is formed sparsely (center portion in FIG.
4
A: also referred to as an “isolated device portion” hereinafter), so that the phenomenon called the dishing, i.e., the surface of the center portion is dented, is caused. Therefore, though the stopper film
71
made of silicon nitride (SiN) has a smaller polishing rate to the silicon oxide film
72
, a capability of the stopper film deteriorates in the portions where the stopper film patterns are sparsely formed, thus the thick stopper film
71
remains in portions where the devices are formed densely, as shown in
FIG. 4B
, if the polishing is carried out to remain the stopper film
71
in the isolated device portion. Then, after the stopper film
71
has been removed, th
Armstrong Westerman Hattori McLeland & Naughton LLP
Clark Sheila V.
Fujitsu Limited
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