Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-12-01
2001-02-13
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S344000, C257S383000
Reexamination Certificate
active
06188114
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuits, and more particularly to insulated-gate field-effect transistors.
2. Description of Related Art
An insulated-gate field-effect transistor (IGFET), such as a metal-oxide semiconductor field-effect transistor (MOSFET), uses a gate electrode to control an underlying surface channel joining a drain and a source. The channel, drain and source are located in a semiconductor substrate, with the substrate being doped oppositely to the drain and source. The gate electrode is separated from the semiconductor substrate by a thin insulating layer such as a gate oxide. The operation of the IGFET involves application of an input voltage to the gate electrode, which sets up a transverse electric field in the channel in order to modulate the longitudinal conductance of the channel.
In typical IGFET processing, the source and drain are formed by introducing dopants of a second conductivity type (P or N) into the semiconductor substrate of a first conductivity type (N or P) using a patterned gate electrode as a mask. This self-aligning procedure tends to improve packing density and reduce parasitic overlap capacitances between the gate electrode and the source/drain regions.
Polysilicon (also called polycrystalline silicon, poly-Si or poly) thin films have many important uses in IGFET technology. One of the key innovations is the use of heavily doped polysilicon as the gate electrode in place of aluminum. Since polysilicon has the same high melting point as a silicon substrate, it can be deposited prior to source and drain formation, and serve as a mask during formation of the source and drain regions by ion implantation. The resistance of polysilicon can be further reduced by forming a silicide on its top surface.
As IGFET dimensions are reduced and the supply voltage remains constant (e.g., 3V), the electric field in the channel near the drain tends to increase. If the electric field becomes strong enough, it can give rise to so-called hot-carrier effects. For instance, hot electrons can overcome the potential energy barrier between the substrate and the gate insulator thereby causing hot carriers to become injected into the gate insulator. Trapped charge in the gate insulator due to injected hot carriers accumulates over time and can lead to a permanent change in the threshold voltage of the device.
A number of techniques have been utilized to reduce hot carrier effects. One such technique is a lightly doped drain (LDD). The LDD reduces hot carrier effects by reducing the maximum lateral electric field. The drain is typically formed by two ion implants. A light implant is self-aligned to the gate electrode, and a heavy implant is self-aligned to the gate electrode on which sidewall spacers have been formed. The spacers are typically oxides or nitrides. The purpose of the lighter first dose is to form a lightly doped region of the drain (or LDD) at the edge near the channel. The second heavier dose forms a low resistivity region of the drain, which is subsequently merged with the lightly doped region. Thereafter, electrical contacts are formed on the heavily doped region. Since the heavily doped region is farther away from the channel than a conventional drain structure, the depth of the heavily doped region can be made somewhat greater without adversely affecting the device characteristics. The lightly doped region is not necessary for the source (unless bidirectional current is used), however LDD structures are typically formed for both the drain and source to avoid the need for an additional masking step.
Disadvantages of LDDs are their increased fabrication complexity compared to conventional drain structures, and parasitic resistance. LDDs exhibit relatively high parasitic resistance due to their light doping levels. During operation, the LDD parasitic resistance can decrease drain current, which in turn may reduce the speed of the IGFET.
Accordingly, there is a need for an IGFET which reduces the parasitic resistance associated with LDDs, and which provides an efficient manner of providing drain and source contacts.
SUMMARY OF THE INVENTION
The present invention provides an IGFET transistor with metal spacers disposed on the drain and source and electrically isolated from the gate electrode. A key feature of the invention is formation of the metal spacers by depositing a blanket layer of conductive metal and then applying an anisotropic etch.
Accordingly, an object of the present invention is to provide metal spacers that can be used as drain and source contacts. Another object of the invention is to provide metal spacers that can increase the lateral conductivity of lightly doped regions, thereby significantly reducing the resistance between heavily doped regions and the channel.
According to one aspect of the invention, an IGFET includes a gate insulator on a semiconductor substrate, a gate electrode on the gate insulator, sidewall insulators adjacent to opposing edges of the gate electrode, metal spacers adjacent to the sidewall insulators and electrically isolated from the gate electrode, and a drain and source in the substrate that contact the metal spacers. If desired, the metal spacers can contact lightly and heavily doped drain and source regions. In this manner, the metal spacers increase the lateral conductivity of the lightly doped regions, and provide drain and source contacts electrically coupled to the heavily doped regions. The sidewall insulators can be oxide spacers that extend to the substrate and cover opposing edges of the gate insulator. Alternatively, the sidewall insulators can be oxides or nitrides grown or deposited on the edges of the gate electrode and vertically spaced from the substrate, so that the metal spacers contact portions of the drain and source underlying the sidewall insulators. Preferably, the gate electrode is polysilicon, the metal spacers are a highly conductive metal such as aluminum, tungsten, titanium, cobalt, or combinations thereof, and the sidewall insulators are sufficiently thick to prevent the metal spacers from diffusing into the gate electrode.
Another aspect of the invention is a method of forming an IGFET with a metal spacers, comprising the steps of forming a gate insulator on a semiconductor substrate, forming a gate electrode on the gate insulator, forming sidewall insulators adjacent to opposing edges of the gate electrode, forming a drain and source in the substrate, and then forming metal spacers on the substrate and adjacent to the sidewall insulators such that the metal spacers contact portions of the drain and source and are electrically isolated from the gate electrode. In this manner, the metal spacers are formed after a high temperature anneal activates the drain and source
A first embodiment of the method includes implanting lightly doped drain and source regions using the gate electrode as an implant mask, forming sidewall insulators adjacent to edges of the gate electrode, implanting heavily doped drain and source regions using the sidewall insulators and gate electrode as an implant mask, applying a thermal cycle to drive-in and activate the drain and source, and then forming the metal spacers.
A second embodiment of the method includes implanting heavily doped drain and source regions using the gate electrode as an implant mask, forming the sidewall insulators adjacent to edges of the gate electrode, applying a thermal cycle to drive-in and activate the drain and source, and then forming the metal spacers.
A third embodiment of the method includes forming insulative spacers adjacent to edges of the gate electrode, implanting heavily doped drain and source regions using the insulative spacers and gate electrode as an implant mask, applying a thermal cycle to drive-in and activate the drain and source, and then forming the metal spacers.
An advantage of the invention is that the metal spacers are formed directly on underlying portions of the drain and source, and therefore provide low resistance drain and sour
Dawson Robert
Fulford Jr. H. Jim
Gardner Mark I.
Hause Frederick N.
Michael Mark W.
Advanced Micro Devices , Inc.
Crane Sara
Odozynski John A.
Skjerven Morrill & MacPherson LLP
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