Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2000-09-01
2001-11-13
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S108000, C438S109000, C438S127000, C438S128000, C438S129000
Reexamination Certificate
active
06316286
ABSTRACT:
FIELD OF INVENTION
This invention relates to an improved method of equalizing device heights on a chip and more particularly for planarizing device heights in flip-chip bump bonded chips.
BACKGROUND OF INVENTION
Hybrid CMOS silicon (Si) and gallium arsenide (GaAs) chip technology, also known as flip-chip, has been developed that allows for direct optical input/output from fiber bundles onto logic circuits. The integration of flip-chip technology with electronics is not limited to Silicon CMOS. The integration process would be the same using other substrates, integrated circuits, etc., such as silicon-germanium, gallium arsenide or other semiconductors, including binary, ternary and quaternary compounds. Silicon CMOS is the most advanced today for many applications but the integration of optoelectronic devices with silicon has proved to be problematic for several reasons. Silicon does not have the band-gap structure that supports the generation of light. In addition, there has been limited success in growing epitaxial layers of III-V materials that do support light emission, such as gallium arsenide (GaAs) or indium phosphide (InP), on silicon substrates because of problems including the lattice mismatch. If a III-V device is to be attached to a silicon substrate it must be grown on a separate substrate comprised of an appropriate material and later attached to the silicon. It is desirable to have multiple types of photonic devices, such as emitters and detectors, integrated onto the same silicon substrate. These devices would be co-located on the silicon and possibly interdigitated. Having very different functions, different photonic devices also have very different eptaxial layer construction. It is not economically feasible for two such dissimilar devices to be grown on the same substrate and so it is necessary that separate growth steps be performed to fabricate each device type. It is further desirable that the final height of the photonic devices be controlled during the attachment process. That is, the final relative height between devices must be predetermined and achievable. In many applications, the interdigitized array of photonic devices must be coplanar. Coplanarity is necessary to insure proper optical coupling between the photonic array and the fiber optic bundle or waveguide. One approach to this problem is to artificially fabricate photonic devices that all have the same thickness or physical dimensions. The problem with this solution is that high frequency performance of the detector devices will be compromised since carriers have to transport through extra material. The time/material required for the growth process, molecular beam epitaxy (MBE), or organometallic chemical vapor deposition (OMCVD) of these additional layers can be cost prohibitive.
SUMMARY OF THE INVENTION
It is therefore an object of this invention to provide an improved method of equalizing device heights on a chip.
It is a further object of this invention to provide such a method which planarizes device heights in flip-chip bump bonded chips.
It is a further object of this invention to provide such a method which uses solder bumps to compensate for device height differentials.
It is a further object of this invention to provide such a method which allows each device to be fabricated independently for optimum performance without the need to achieve a fixed height constraint.
It is a further object of this invention to provide such a method which allows different photonic devices to be fabricated on a silicon substrate.
This invention results from the realization that an improved method of equalizing device heights on a chip can be achieved by providing on a first chip an array of first devices having a predetermined height including dummy devices with bonding bumps, bump bonding the first chip to a second chip which has its own bonding bumps, removing the dummy devices to create holes containing the double bumps remaining after removal of the dummy devices, providing on a third chip an array of second devices having a lower height and having bonding bumps which match those in the holes and bump bonding the third chip to the second chip with the second devices in the holes and the bonding bumps on the second devices combining with the double bumps in the holes to equalize the height of the first and second devices.
This invention features a method of equalizing device heights on a chip including providing on a first chip an array of first devices having a predetermined height including dummy devices with bonding bumps. The first chip is bump bonded to a second chip which also has bonding bumps by engaging the bonding bumps on the first chip with those on the second chip. The dummy devices are removed to create holes containing the multiple bumps previously associated with the dummy devices. A third chip is provided with an array of second devices having a lower height than the first devices and having bonding bumps which match those in the holes. The third chip is bump bonded to the second with the second devices in the holes and the bonding bumps on the second devices combining with the multiple bumps in the holes to equalize the height of the first and second devices.
In a preferred embodiment, the voids between the first and second chips may be filled with an underfill. The first chip may be removed except for the first devices. The underfill associated with the dummy devices may be removed and the underfill associated with the remaining devices preserved. The voids between the chips associated with the second devices may also be filled with an underfill. The devices may be photonic devices. The first and third chips may include gallium arsenide, the second chip may include silicon. The second chip may include an application specific integrated circuit. One of the first and second devices may include light emitters and the other light detectors. One of the first and second devices may include vertical cavity surface emitting lasers and the other p-i-n diodes. The dummy devices may be the same as the first devices. The first and third chips may include indium phosphate or indium gallium arsenide nitride. The second chip may include silicon germanium or gallium arsenide. The underfill may include an epoxy or a photoresist. The first chip may be removed except for the first devices and the third chip may be removed except for the second devices.
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Asmus Scott J.
Maine Vernon C.
Niebling John F.
TeraConnect, Inc.
Zarneke David A
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