Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-07-13
2001-11-20
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S773000
Reexamination Certificate
active
06320225
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a semiconductor device, and more particularly to a method for forming a silicon on insulator structured substrate with body-contacts under the gate conductor.
2. Description of Related Art
In the silicon on insulator (“SOI”) art, it is well recognized that the resistance-capacitance (“RC”) delay associated with body-contacts to wide channel MOSFETS limits the effectiveness of body-charge equilibrium at high-speeds. This occurs because the charge associated with the SOI body must traverse the half-width of the MOSFET. The resistance of the path increases with increasing width of the main channel until RC time constant of the body contact becomes a significant factor, which may cause unstable device behavior. The increased resistance degrades the ability of the device to remove hole charge (majority carriers in an NMOSFET) because in a wide channel device the holes leaving the body must traverse a long path. An analogous situation exists in SOI PMOSFETS, where excess electrons in the body comprise the majority carrier charge to be removed. Excess holes remain in the body of the device causing the device to latch up and lose gate control. With the need for wide devices in the semiconductor art, it is difficult to achieve a stable device.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a method and structure for efficient body-contact operation for SOI MOSFETS of any width operating at high-speeds.
It is another object of the present invention to provide a method and structure for SOI body-contacts that are easily integrated into existing SOI processes.
It is another object of the present invention to enhance the ability of a wide body SOI MOSFET to remove excess majority carrier charge.
A further object of the invention is to provide a method and structure for an SOI body-contact that requires only one additional masking level.
It is yet another object of the present invention to provide a method and structure for an SOI body-contact that consumes no additional real estate on a substrate.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
SUMMARY OF THE INVENTION
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to a method of forming a silicon on insulator body contact under a gate conductor on a silicon on insulator substrate. In the preferred embodiment, the method comprises depositing a first insulating layer, such as tetraethoxysilane, over the silicon on insulator substrate. An opening is formed in the first insulating layer and extends through the first insulating layer, through the gate conductor to the semiconductor substrate. The opening has an insulating spacer on each of its sidewalls which are adjacent the first insulating layer and gate conductor regions. In the preferred embodiment, the insulating spacers are silicon nitride. A layer of a first conductive material, preferably P+ polysilicon, is deposited in the opening. In the preferred embodiment, the first conductive material layer is recessed so that the top of the first conductive material layer maintains electrical contact with a monocrystalline semiconductor layer of the silicon on insulator substrate. It is also preferred to deposit a second insulating material, preferably tetraethoxysilane, over the first conductive material layer.
In the preferred embodiment the method also comprises depositing a layer of a second conductive material, such as polysilicon, over the second insulating layer and depositing a layer of a metal such as tungsten, titanium or cobalt over the second conductive material layer. In the preferred embodiment, the metal layer is reacted with the second conductive material layer to form a silicide that is self aligned to the gate conductor.
In another aspect of the preferred embodiment, the method includes implanting a dopant, such as boron, into the semiconductor substrate at the bottom of the body-contact via.
In another aspect, the invention comprises a body contact structure under a gate conductor on a silicon on insulator substrate. The preferred embodiment comprises a first insulating layer, such as tetraethoxysilane, lying over, and in electrical contact with, the gate conductor. In the preferred embodiment, there is an opening in the substrate which extends from a top surface of the first insulating layer, through the gate conductor to the semiconductor substrate. On each sidewall of the opening, in the area adjacent the first insulating layer and the gate conductor, an insulating spacer is formed. The insulating spacer is preferably a silicon nitride. In the preferred embodiment, the opening is filled with a layer of a second insulating material, preferably tetraethoxysilane, on top of the first conductive material layer, which is preferably P+ polysilicon.
In the preferred embodiment, a second conductive material layer, such as polysilicon, is over the second insulating layer. In the preferred embodiment, a salicide is found over the gate conductor.
It is also preferred to have a dopant, such as boron, implanted at the bottom of the opening.
REFERENCES:
patent: 6175135 (2001-01-01), Liao
Hargrove Michael J.
Mandelman Jack A.
DeLio & Peterson LLC
International Business Machines - Corporation
Prenty Mark V.
Reynolds Kelly M.
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