Method of forming a multi-layered dual-polysilicon structure

Details Method of forming a multi-layered dual-polysilicon structure Method of forming a multi-layered dual-polysilicon structure

1999-04-22

2001-02-20

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S152000, C438S594000, C438S734000

Reexamination Certificate

active

06191017

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to integrated circuits and, more specifically, to a method of forming a multi-layered dual-polysilicon semiconductor structure, and devices and integrated circuits formed in accordance therewith.
BACKGROUND OF INVENTION
Multi-layered structures with dual layers of polysilicon over oxide layers of differing thickness have many uses in integrated circuits. Such structures are particularly useful for construction of MOS integrated circuits including Dynamic Random Access Memory (DRAM) cells and Static Random Access Memory (SRAM) cells, for example. The methods of manufacturing multi-layered dual-polysilicon structures currently require multiple and sometimes complicated processing steps including implantation barrier deposition and removal, polysilicon deposition, patterning, and etching.
These multiple, and sometimes repetitive, processing steps increase the fabrication time and expense of manufacturing integrated circuits and semiconductor devices. Moreover, fabrication tolerances are controlled in part by the type and number of processing steps. Thus, fewer and simpler processing steps will yield tighter manufacturing tolerances and denser integrated circuits and semiconductor devices.
Thus there exists a need in the art for a method of forming a multi-layered dual-polysilicon structure that overcomes the above-described shortcomings.
SUMMARY OF THE INVENTION
The present invention is directed to a method that allows formation of dual polysilicon structures prior to formation of an ion implantation barrier structure and that requires fewer steps, is more economical, and permits fabrication of more compact semiconductor circuits and devices than prior art methods.
A preferred embodiment of the present invention is directed to a method of forming a multi-layered dual-polysilicon semiconductor structure. First and second trenches of differing depths are formed in a first insulating layer on the substrate. A second insulating layer is formed in the first and second trenches. Thereafter, polysilicon material is formed in the first and second trenches such that the first and second trenches are substantially filled with the polysilicon material. A portion of the polysilicon material is removed from the first and second trenches so that the top surface of the first insulating layer and a top surface of the polysilicon material are not co-planar (i.e., are not at the same height). An implantation barrier is formed on the polysilicon material in the first and second trenches and processed so that a top surface of the insulating barrier is substantially co-planar with the top surface of the first insulating layer. Ton implantation is then performed to form LDD regions and source and drain regions.
The present invention is also directed to integrated circuits and semiconductor devices constructed in accordance with the above-described method.
Other objects and features of the present invention will become apparent from the following detailed description, considered in conjunction with the accompanying drawing figures. It is to be understood, however, that the drawings, which are not to scale, are designed solely for the purpose of illustration and not as a definition of the limits of the invention, for which reference should be made to the appended claims.


REFERENCES:
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patent: 5926700 (1999-07-01), Gardner et al.
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patent: 6080625 (2000-06-01), Chittipeddi et al.
patent: 6083845 (2000-07-01), Yang et al.
patent: 6096584 (2000-08-01), Ellis-Monaghan et al.
patent: 6117732 (2000-09-01), Chu et al.
patent: 6121128 (2000-09-01), Hakey et al.

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