Static semiconductor memory device with expanded operating...

Details Static semiconductor memory device with expanded operating... Static semiconductor memory device with expanded operating...

2000-05-04

2001-11-13

Ngô, Ngân V. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S379000, C257S903000, C257S904000, C365S189050, C365S189080, C365S189090, C365S205000, C365S230080

Reexamination Certificate

active

06316812

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to structures of static semiconductor memory devices having memory cells including MOS transistors and, more specifically to a structure of a memory cell power supply circuit for a static semiconductor memory device.
2. Description of the Background Art
FIG. 16
is a circuit diagram showing a structure of a memory cell for a static random access memory (hereinafter abbreviated as an SRAM) including a conventional MOS transistors.
Referring to
FIG. 16
, the conventional memory cell includes a P channel MOS load transistor P
11
and an N channel MOS driver transistor N
11
connected in series between power supply potentials Vcc and ground potentials GND as well as a P channel MOS load transistor P
12
and an N channel MOS driver transistor N
12
connected in series between power supply potentials Vcc and ground potentials GND. A connection node between P channel MOS load transistor P
11
and N channel MOS driver transistor N
11
is referred to as a storage node nm
1
, whereas a connection node between P channel MOS load transistor P
12
and N channel MOS driver transistor N
12
is referred to as a storage node nm
2
.
Transistors P
11
and N
11
have their gates connected to storage node nm
2
, and transistors P
12
and N
12
have their gates connected to storage node nm
1
.
The conventional memory cell further includes an N channel MOS access transistor Tra
1
arranged between a bit line BL and storage node nm
1
and having its gate potential controlled by a word line WL, and an N channel MOS access transistor Tra
2
arranged between storage node nm
2
and a bit line /BL and having its gate potential controlled by word line WL.
Now, each operating state of the memory cell will be described in terms of a current flowing from a memory cell power supply source, i.e., a power supply source supplying a power supply potential to sources of load PMOS transistors P
11
and P
12
of the memory cell.
FIG. 17
is a diagram shown in conjunction with a current flowing to all memory cells in a stand-by mode or to the memory cell in a non-selected row in a reading/writing operation mode.
In this state, N channel MOS access transistors Tra
1
and Tra
2
are in a cut-off state because word line WL is at an “L” level.
P channel MOS load transistor P
11
on the side of storage node nm
1
with “H” level data is in a conductive state, whereas N channel MOS driver transistor N
11
is in the cut-off state. Thus, only a leakage current in an off state (hereinafter referred to as an off leakage current) of N channel MOS driver transistor N
11
is applied from memory cell power supply source Vcc to the memory cell.
Further, N channel MOS driver transistor N
12
on the side of node nm
2
with “L” level data is in the conductive state, whereas P channel MOS load transistor P
12
is in the cut off state. Thus, only an off leakage current of P channel MOS transistor P
12
is applied from the memory cell power supply source to the memory cell.
FIG. 18
is a diagram shown in conjunction with a current flowing to a memory cell in a selected row during a reading operation as well as in a selected row and non-selected column during a writing operation.
The portion on the side of storage node nm with the “H” level data will be described.
P channel MOS load transistor P
11
is in the conductive state, whereas N channel MOS driver transistor N
11
is in the cut off state. Thus, only an off leakage current of N channel MOS transistor N
11
is applied from the memory cell power supply source to the memory cell.
Although word line WL is at the “H” level, a gate, drain, and source of N channel MOS access transistor Tra
1
are all at the “H” level as bit line BL is also precharged to the “H” level. Thus, a current is not supplied between the memory cell and bit line BL.
Next, the portion on the side of storage node nm
2
with the “L” level data will be described.
N channel MOS driver transistor N
12
is in the conductive state, whereas P channel MOS load transistor P
12
is in the cut off state. Thus, only an off leakage current of P channel MOS load transistor P
12
is applied from the memory cell power supply source to the memory cell.
As word line BL is at the “H” level and the bit line is also precharged to the “H” level, a gate and drain of N channel MOS access transistor Tra
2
are both at the “H” level and a source thereof is at the “L” level. Thus, a column current Ic is supplied from bit line /BL toward storage node nm
2
as indicated by an arrow in FIG.
18
and then supplied to ground GND via driver transistor Tra
2
.
However, a power supply potential for precharging bit line /BL to the “H” level and a power supply potential to the memory cell are supplied from separate paths, so that only the off leakage current of P channel MOS load transistor P
12
is applied from the memory cell power supply source.
FIG. 19
is a diagram shown in conjunction with a current supplied to a memory cell to be rewritten in a selected row and in a selected column during a writing operation. First, the portion on the side to be changed from the “L” level to the “H” level (on the side of storage node nm
1
) will be described.
P channel MOS load transistor P
11
, initially in the cut off state, is brought into the conductive state as the level of storage node nm
2
which is connected to P channel MOS transistor P
12
paired with P channel MOS load transistor P
11
is changed from the “H” to “L” level.
N channel MOS driver transistor Nil, initially in the conductive state, is brought into the cut off state as the level of storage node nm
2
on the side of N channel MOS driver transistor N
12
paired with N channel MOS driver transistor N
11
is changed from the “H” to “L” level.
As word line WL is at the “H” level and bit line BL is precharged to the “H” level, initially, a gate and drain of N channel MOS access transistor Tra
1
are both at the “H” level and a source thereof is at the “L” level. Thus, a current Ic is supplied from bit line BL to storage node nm
1
as indicated by an arrow shown in
FIG. 19
, and supplied to ground GND via a driver transistor. However, when N channel MOS driver transistor N
11
is brought into the cut off state, the flow of current Ic sooner or later stops.
A power supply potential for precharging bit line BL to the “H” level and a power supply potential of the memory cell are supplied by separate paths, so that only an off leakage current of P channel MOS load transistor P
11
is initially supplied from the memory cell power supply source and only an off leakage current of N channel MOS transistor N
11
is supplied from the memory cell power supply source after the writing operation.
Next, the portion on the side to be written from the “H” to “L” level (on the side of storage node nm
2
) will be described.
P channel MOS load transistor P
12
is initially in the conductive state, but brought into the cut off state as the level of storage node nm
1
on the other side is changed from the “L” to “H” level.
N channel MOS driver transistor N
12
is initially in the cut off state, but brought into the conductive state as the level of storage node nm
1
on the other side is changed from the “L” to “H” level.
Word line WL is at the “H” level, and bit line /BL has been brought down to be “L” level by a writing driver. Thus, a gate and drain of N channel MOS access transistor Tra
2
are both at the “H” level, and a source thereof is at the “L” level, so that a current Imc is supplied from the memory cell power supply source to the storage node via a load transistor and further supplied to bit line /BL as indicated by an arrow. The flow of current Imc sooner or later stops as P channel MOS load transistor P
12
is brought into the cut off state.
Such a current Imc flowing from the memory cell power supply source to the memory cell is only generated for the memory cell to be rewritten in the selected row and in the selected column during the writing operation. In addition, such a significant current Imc is generated after word

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