Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-01-06
2001-12-11
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S413000, C257S900000
Reexamination Certificate
active
06329695
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to an improved series-connected transistor architecture and method for producing this architecture by forming merged sidewall spacers.
2. Description of the Relevant Art
In integrated circuit fabrication, transistors are fabricated upon and within a semiconductor substrate, and subsequently interconnected to form circuits. In digital metal-oxide-semiconductor (MOS) integrated circuit fabrication, for example, MOS field-effect transistors (MOSFETs) are typically connected into circuits which perform logical operations, such as AND and OR functions. An example of an n-type MOS (NMOS) circuit which performs an inverting AND, or NAND, operation is shown in FIG.
1
. Transistor
10
has its source connected to ground, its gate connected to input voltage A, and its drain connected to the source of transistor
12
. The gate of transistor
12
is in turn connected to input voltage B, and the drain of transistor
12
is connected to the source of load transistor
14
. Output voltage V
0
is taken at the drain of transistor
12
.
A partial cross-sectional view of the transistors of
FIG. 1
formed upon and within semiconductor substrate
16
is shown in FIG.
2
. Because transistors
10
,
12
, and
14
are connected in series, with the drain of one connecting to the source of another, it is important not to form isolation regions between them. Isolation regions
18
are therefore arranged only at the outside of the group of transistors. To fabricate the transistors of
FIG. 2
, a gate dielectric layer is formed on substrate
16
, and a layer of a conductive material is subsequently deposited. These layers are subsequently patterned to form gate dielectrics
20
and gate conductors
22
. A dielectric layer is subsequently deposited over the substrate and anisotropically etched to form dielectric spacers
24
on sidewalls of gate conductors
22
. Before spacer formation, an impurity distribution may be introduced into substrate
16
, self-aligned to sidewalls of gate conductors
22
. Subsequent to spacer formation, a somewhat more heavily-doped impurity distribution may be introduced, self-aligned to exposed lateral surfaces of spacers
24
. These two impurity distributions combine to form drain region
26
of transistor
14
, merged source/drain regions
28
, and source region
30
of transistor
10
. Formation of spacers
24
may be advantageous for many reasons including the ability to form shallow lightly-doped drain (LDD) regions under the spacers which may lower the maximum electric field developed at the drain end of the channel. This lowered electric field may reduce the severity of hot-carrier effects such as avalanche breakdown at the drain/substrate junction and injection of carriers into the gate dielectric.
Spacers
24
may also be advantageous by providing isolation between the source/drain and gate regions so that a salicide process may be performed. In a salicide process, a metal film is blanket-deposited over the exposed surfaces of the transistor after formation of the source and drain regions. The transistor is then subjected to a heating process which causes a reaction between the metal and silicon that the metal is in contact with, forming a silicide on the silicon surfaces. Unreacted metal is then removed, leaving the silicide covering the gate, source, and drain regions. In forming the transistors shown in
FIG. 2
, a salicide process may be used to form gate silicides
32
, drain silicide
34
, merged source/drain silicides
36
, and source silicide
38
.
A pervasive trend in modern integrated circuit manufacture is to produce transistors having feature sizes as small as possible. To achieve a high density integrated circuit, features such as the gate conductor, source/drain junctions, and interconnect to the junctions must be as small as possible. Many modern day processes employ features which have less than 1.0 &mgr;m critical dimension. As feature size decreases, the resulting transistor size as well as the spacing between transistors also decreases. Fabrication of smaller transistors allows more transistors to be placed on a single monolithic substrate, thereby allowing relatively large circuit systems to be incorporated on a single, relatively small die area.
The benefits of high density circuits can only be realized if advanced processing techniques are used. For example, semiconductor process engineers and researchers regularly consider the benefits of electron beam lithography and x-ray lithography to achieve the lower resolutions needed for submicron features. To some extent, wet etching has given way to a more advanced anisotropic (dry etch) technique. Furthermore, silicides have replaced higher resistivity contact structures mostly due to the lower resistivity needed when a smaller contact area is encountered.
In addition to the processing techniques used, the layout of the specific circuits being fabricated may have an effect on the circuit density. This is illustrated by
FIGS. 1 and 2
, which show, for example, that transistors which are connected in series can be spaced more closely than those which must be separated by isolation regions. The density of the series-connected transistors is still limited, however, both by the space needed between gate conductors to accommodate sidewall spacers and by the space needed to form source/drain silicide contacts. It would therefore be desirable to develop a method for increasing the density of series-connected transistors.
SUMMARY OF THE INVENTION
The problems outlined above are in large part addressed by reducing the spacing between gate conductors of series-connected transistors for which no contact is made to the merged series source/drain (SSD) region. Isolation regions may be formed in a semiconductor substrate to define active regions such that each group of series-connected transistors shares an active region. Gate dielectric and conductive layers are subsequently formed on the semiconductor substrate. The conductive layer is patterned in such a way that gate conductors on either side of a merged SSD region are spaced closer together than gate conductors on either side of a series-connected source/drain region having a contact. In an embodiment of the method and resulting series transistor architecture, the spacing between facing sidewalls of the more closely spaced gate conductors is smaller than about twice the anticipated sidewall spacer width.
After patterning of the gate conductors, a shallow impurity distribution is introduced into the substrate, masked by the gate conductors. A conformal dielectric layer is subsequently blanket-deposited over the substrate and gate conductors. The conformal dielectric layer is then anisotropically etched so that conventional dielectric spacers are formed on sidewalls of the more widely spaced gate conductors. In the case of the closely spaced gate conductors, however, the spacers in the region between these closely spaced conductors are merged, such that a continuous dielectric region is formed. This occurs as a result of the small spacing between these conductors.
After the spacer formation, a deeper, somewhat more heavily doped impurity distribution may be introduced, masked by the gate conductors and dielectric spacers. For the more widely spaced gate conductors, this second impurity distribution combines with the distribution introduced before spacer formation to form source and drain regions having shallow “LDD” portions under the spacers. In the case of the closely spaced gate conductors, the continuous dielectric between these conductors prevents introduction of the second, deeper impurity distribution between the conductors. The merged SSD region between the more closely spaced gate conductors is therefore formed using only the first, shallow impurity introduction. A major reason for including a deeper, somewhat more heavily doped source or drain portion is believed to be formation of a low-resistance contact to the re
Bourland Steven E.
Duane Michael P.
Advanced Micro Devices , Inc.
Conley & Rose & Tayon P.C.
Daffer Kevin L.
Loke Steven
Vu Hung Kim
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