Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-08-19
2001-11-13
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C700S110000, C700S097000, C700S121000, C378S035000, C382S172000
Reexamination Certificate
active
06317866
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a pattern data preparing method used in a charged particle beam drawing apparatus that prepares a micropattern with a charged particle beam and, more particularly, to a pattern data preparing method of obtaining highly reliable pattern data.
2. Description of the Prior Art
Along with the development of LSIs, patterns used in semiconductor devices continue to shrink rapidly in feature size. The charged particle beam drawing method using a charged particle beam is an effective method capable of forming a pattern with a size of 0.25 &mgr;m or less which will be needed in the future. As a charged particle beam drawing apparatus, a variable shaping type electron beam drawing apparatus as shown in
FIG. 1
is used. According to this apparatus, an electron beam is shaped to have a rectangular spot with a first aperture
3
and a second aperture
6
. A resultant electron beam
50
B is radiated onto a semiconductor wafer
11
coated with a resist, thereby forming a micropattern.
Referring to
FIG. 1
, an electron beam
50
emitted from an electron gun
1
passes through a blanking electrode
2
, the first aperture
3
, a shaping lens
4
, a shaping deflector
5
, the second aperture
6
, a reduction lens
7
, a main deflector
8
, a sub-deflector
9
, and a projection lens
10
to irradiate the semiconductor wafer
11
on a stage. A square opening
3
A is formed in the first aperture
3
to form a rectangular beam
50
A. The rectangular beam
50
A passes through an opening
6
A of the second aperture
6
to have a small-size square beam spot. Shot (one exposure operation) is repeated with this small-size electron beam
50
B to form one latent image pattern in the resist on the semiconductor wafer
11
.
A storage unit
15
stores figure data. The figure data is read by a computer
14
and temporarily stored in a figure data memory
17
. The drawing apparatus reads this figure data as required, converts it into a control signal with a controller
16
, and controls the blanking electrode
2
, the shaping deflector
5
, the main deflector
8
, and the sub-deflector
9
to draw a figure. This figure data is obtained by subjecting CAD data to overlapping removal, proximity effect correction, and the like and converting the resultant CAD data into a specific format for the drawing apparatus. Japanese Unexamined Patent Publication No. 7-288224 describes a method that uses interlayer calculation in order to prevent occurrence of deformation of the pattern on the cell boundary when enlargement and reduction are performed while retaining the hierarchical cell structure. Japanese Unexamined Patent Publication No. 4-372155 describes a method of comparing and verifying the LSI layout pattern, outputting the coordinates of different points, and correcting the layout pattern by using an editor.
In recent years, as the integration degree of semiconductor devices as objects on which patterns are to be drawn increases, the number of patterns to be drawn becomes very large, and the amount of data handled by the conversion software also increases very much. For this reason, batch processing is widely performed. More specifically, a semiconductor chip is divided, and conversion is performed in units of batch process regions. After conversion for all the regions is ended, obtained data are combined to prepare 1-chip data. When this batch processing is performed, it is difficult to handle a pattern crossing the boundary or boundaries between more than one region. Sometimes pattern losses, generation of a redundant pattern, or positional shifts may occur in the data after conversion. If data having such a defect is directly used for drawing, it produces interconnect disconnections, short-circuits, or the like to lead to a decrease in yield of devices. Therefore, it is important to verify whether converted data is different from the original CAD data. Japanese Unexamined Patent Publication No. 7-288224 provides no means for verifying such defects of the pattern data. According to Japanese Unexamined Patent Publication No. 4-372155, the layout pattern is directly corrected with reference to the coordinates of different points, and the corrected data is converted into drawing data again. Accordingly, a very long process time is required to obtain normal drawing data. Since correction is manually performed by the operator, a new defective portion may be undesirably formed during the course of correction.
SUMMARY OF THE INVENTION
The present invention has been made in consideration of the above situation in the prior art, and has as its object to provide a method of preparing charged particle beam drawing data, which can quickly correct any calculation error that occurs when converting CAD data into pattern data without forming a new defective portion, and a recording medium on which a program thereof is recorded.
In order to achieve the above object, according to the first aspect of the present invention, there is provided a charged particle beam drawing data preparing method of preparing drawing pattern data used in a charged particle beam drawing apparatus that forms a micropattern with a charged particle by converting CAD data, the method comprising the steps of verifying, by using interlayer calculation, whether a difference exists between the CAD data and the drawing pattern data, and when it is verified in the verifying step that a difference exists between the CAD data and the drawing apparatus pattern data, generating drawing pattern data that compensates for this difference by using interlayer calculation.
According to the second aspect of the present invention, there is provided a charged particle beam drawing data preparing method of preparing pattern data used in a charged particle beam drawing apparatus that forms a micropattern with a charged particle, wherein when a difference exists between original CAD data and drawing apparatus pattern data, pattern data that compensates for this difference is generated by using interlayer calculation.
According to the third aspect of the present invention, there is provided a charged particle beam drawing data preparing method according to the second aspect, comprising, as means for generating the compensation pattern data, the steps of performing an exclusive logical sum operation (eor) between the original CAD data and the drawing apparatus pattern data having pattern loss, and outputting, as drawing pattern data, both the drawing apparatus pattern data having the pattern loss and pattern data obtained by the exclusive logical sum operation.
According to the fourth aspect of the present invention, there is provided a charged particle beam drawing data preparing method according to the second aspect, comprising, as means for generating the compensation pattern data, the steps of performing an exclusive logical sum operation (eor) between the original CAD data and the drawing apparatus pattern data having a pattern shift, performing a logical product operation (and) between the original CAD data and pattern data obtained by the exclusive logical sum operation, performing a logical difference operation (sub) between the drawing apparatus pattern data having the pattern shift and the pattern data obtained by the exclusive logical sum operation, and outputting, as drawing pattern data, both the pattern data obtained by the logical difference operation and the pattern data obtained by the logical product operation.
According to the fifth aspect of the present invention, there is provided a charged particle beam drawing data preparing method according to the second aspect, comprising, as means for generating the compensation pattern data, the steps of performing an exclusive logical sum operation (eor) between the original pattern data and the drawing apparatus pattern data having a redundant pattern, performing a logical difference operation (sub) between the redundant pattern and the pattern data obtained by the exclusive logical sum operation, and outputting, as drawing pattern
Kik Phallaka
NEC Corporation
Smith Matthew
LandOfFree
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