Ferroelectric memory device

Details Ferroelectric memory device Ferroelectric memory device

1999-03-16

2001-02-20

Mai, Son (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S189090, C365S210130

Reexamination Certificate

active

06191971

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a ferroelectric memory device for storing data according to the state of polarization of a ferroelectric film provided between electrodes of a capacitor and sensing a variation in the bit line potential according to the polarization state of the ferroelectric film to read out stored data.
The ferroelectric memory device is described in, for example, U.S. Pat. No. 4,873,664 Eaton, Jr., “Self Restoring Ferroelectric Memory”, ISSCC 94, pp. 268 to 269, 1994 Tatsumi Sumi et al. “A 256 kb Nonvolatile Ferroelectric Memory at 3V and 100 ns” and the like.
A circuit section constructing the basic portion of the ferroelectric memory device is constructed as shown in
FIG. 1
, for example. In this example, main portions such as memory cells, dummy cells, sense and rewrite amplifier (sense amplifier) and peripheral circuit thereof are extracted and shown. Memory cells MC
1
, MC
2
are respectively formed of ferroelectric capacitors
10
,
11
and selection transistors
14
,
15
, and dummy cells DCa, DCb are respectively formed of ferroelectric capacitors
12
,
13
and selection transistors
16
,
17
. A word line
19
on an i-th row is connected to the gate of the selection transistor
14
of the memory cell MC
1
and a plate line
23
on the I-th row is connected to the plate electrode of the ferroelectric capacitor
10
. Likewise, a word line
20
on an (i+1)th row is connected to the gate of the selection transistor
15
of the memory cell MC
2
and a plate line
24
on the (i+1)th row is connected to the plate electrode of the ferroelectric capacitor
11
. Further, a dummy word line a
21
is connected to the gate of the selection transistor
16
of the dummy cell DCa and a dummy plate line a
25
is connected to the plate electrode of the ferroelectric capacitor
12
. In addition, a dummy word line b
22
is connected to the gate of the selection transistor
17
of the dummy cell DCb and a dummy plate line b
26
is connected to the plate electrode of the ferroelectric capacitor
13
.
Ends of the current paths of the selection transistor
14
of the memory cell MC
1
and the selection transistor
17
of the dummy cell DCb are connected to a bit line
27
and ends of the current paths of the selection transistor
15
of the memory cell MC
2
and the selection transistor
16
of the dummy cell DCa are connected to a /bit line (“/” indicates a bar indicating inversion)
28
. When the memory cell MC
1
is selected, the dummy cell DCa is selected, a reference potential generated by the dummy cell DCa is applied to the /bit line
28
and the /bit line
28
is used as a reference bit line for detecting the high level or low level of the bit line
27
. Further, when the memory cell MC
2
is selected, the dummy cell DCb is selected, a reference potential generated by the dummy cell DCb is applied to the bit line
27
and the bit line
27
is used as a reference bit line for detecting the high level or low level of the /bit line
28
.
The sense and rewrite amplifier (sense amplifier)
18
is connected between the paired bit lines
27
and
28
to amplify a potential difference between the paired bit lines
27
and
28
. The paired bit lines
27
and
28
are respectively connected to common readout data line and /data line
303
and
304
via the current paths of transistors
300
and
301
for selecting a column. The gates of the transistors
300
and
301
are connected to a column selection line
302
and a signal amplified by the sense amplifier
18
of a column selected by a column selection signal supplied from a column decoder (not shown) is supplied to the common readout data line and /data line
303
and
304
.
With the above construction, the directions of the electric field and polarization (the directions are the same) of the ferroelectric film of each of the ferroelectric capacitors
10
to
13
are defined as a positive direction if the direction is set from the plate lines
23
,
24
and dummy plate lines
25
,
26
to the bit lines
27
,
28
. In the ferroelectric memory device, a difference (low or high level) occurs in the potential level of the bit line
27
or
28
according to the polarization state (the direction of polarization) of the ferroelectric capacitor
10
or
11
which stores data. The stored data is read out by sensing and amplifying a difference between the potential level of the bit line
27
or
28
and the potential level of the reference bit line
28
or
27
by use of the sense amplifier
18
. More specifically, as shown in the timing chart of
FIG. 2
, the potential of a to-be-selected bit line is previously set at 0 (V) and the potentials of a word line and plate line connected to a to-be-selected memory cell are raised to a high level to select the memory cell (time t1). Then, after the potential of the bit line is changed, the sense amplifier is activated (time t2) so as to set the bit line potential to a high or low level according to the direction of polarization of the ferroelectric capacitor. At this time, a reference potential is generated by selecting the dummy word line a
21
when the word line
19
on the i-th row is selected and by selecting the dummy word line b
22
when the word line
20
on the (i+1)th row is selected.
In this case, assume that the power supply voltage is 3 (V) and the maximum potential of the selected plate line is 3 (V). Further, assume that the maximum potential of the selected word line is boosted to a voltage (for example, 4.5 (V)) for compensating for a drop in the threshold voltage of the selection transistor so as to permit the high potential level of the bit line to be transmitted to the ferroelectric capacitor.
When the direction of polarization of the ferroelectric capacitor in the selected memory cell MC is an upward direction (from the plate line side to the bit line side), the polarization is not reversed since the directions of the electric field and polarization are the same. A variation in the polarization occurring in the cell at this time is shown in FIG.
3
A. In this case, since the amount of charges discharged from the cell is small, the bit line potential level is low. On the other hand, when the direction of polarization is a downward direction (from the bit line side to the plate line side), the polarization is reversed since the directions of the electric field and polarization are opposite to each other. A variation in the polarization occurring in the cell at this time is shown in FIG.
3
B. In this case, since the amount of charges discharged from the cell is large, the bit line potential level is high. Therefore, a level difference between the potentials of the paired bit lines
27
and
28
can be sensed by use of the sense amplifier
18
by generating a reference potential in a condition that the areas of the ferroelectric capacitors
12
,
13
in the dummy cells DCa, DCb are set m (>1) times those of the ferroelectric capacitors
10
,
11
in the memory cells MC
1
, MC
2
and setting the potential of one of the bit lines which is used as a reference bit line to an intermediate level between the high and low potential levels of the other bit line from which data is read out. However, in this case, it is necessary to generate a driving pulse for the dummy word lines a
21
, b
22
and dummy plate lines a
25
, b
26
so that the ferroelectric capacitors
12
,
13
of the dummy cells DCa, DCb will be always operated without polarization reversal.
In
FIGS. 3A and 3B
, the polarization becomes “0” when the voltage is set to one of two voltage levels which are each called a coercive voltage. When the voltage is set at “0”, two polarization levels are present and they are called remnant polarization.
In the conventional ferroelectric memory device, it is known that the characteristic of the ferroelectric capacitor varies depending on the position in which the chip is formed in the wafer and the high level and low level of the bit line vary according to the polarization state.
FIG. 4
shows the relation between the high level and l

Affiliated with

Also associated with

Rating

Ferroelectric memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Ferroelectric memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Ferroelectric memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2599332