Method for fabricating a semiconductor device

Details Method for fabricating a semiconductor device Method for fabricating a semiconductor device

2001-01-02

2001-12-25

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S231000, C438S299000

Reexamination Certificate

active

06333249

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for forming a gate electrode by a semi-damascene process to prevent a metal layer from being oxidized when a gate electrode having a layered structure of the metal layer and a polysilicon layer is formed in a CMOS transistor of a high integrated device such as a DRAM cell.
2. Background of the Related Art
In a prior art method for fabricating a dual gate electrode device, a n
+
gate and a p
+
gate are respectively deposited and patterned on an upper portion of an undoped polysilicon layer using a mask and dual implantation method (n
+
:As.P, p
+
:B.BF
2
), or an in-situ doping method.
The dual implantation method has a relatively simple process, but it is difficult to achieve high doping levels. Also, in the dual implantation method, it is likely that gate depletion will occur as a result of the dopant profile characteristics.
In the in-situ doping method it is necessary to set up respective process steps, because the gate electrodes for the n
+
and p
+
polysilicon layers should be formed separately.
A prior art method for fabricating a semiconductor device will be described with reference to the accompanying drawings.
FIGS. 1A
to
1
C are sectional views showing prior art process steps for fabricating a semiconductor device.
As shown in
FIG. 1A
, a device isolation film
12
is formed to define active regions on a semiconductor substrate
10
.
A p-type well is formed in a portion where an NMOS device will be formed (NMOS region I), and an n-type well is formed in a portion where a PMOS device will be formed (region II).
Subsequently, a gate insulating film
14
is formed on the upper portion of the entire surface, and a polysilicon layer is formed on the gate insulating film
14
. A first photoresist film pattern is then formed on the polysilicon layer to expose the NMOS region I. An n
+
polysilicon layer is formed by an n-type impurity ion implantation using the first photoresist film pattern as an ion implantation mask.
Afterwards, the first photoresist film pattern is removed. A second photoresist film pattern is then formed on the polysilicon layer to expose the PMOS region II. A p
+
polysilicon layer
16
a
is formed by a p-type impurity ion implantation using the second photoresist film pattern as an ion implantation mask. Then, the second photoresist film pattern is removed.
Next, a diffusion prevention film
18
a,
a metal layer
20
a,
and a mask insulating film
22
a
are sequentially formed on the upper portion of the entire surface to form a layered structure.
As shown in
FIG. 1B
, the layered structure and the polysilicon layer into which the impurity ions were implanted are etched using a gate electrode mask that which protects a portion where a gate electrode will be formed as an etching mask. Thus, a mask insulating pattern
22
b,
a metal layer pattern
20
b,
a diffusion prevention film pattern
18
b,
an n
+
gate electrode
15
b,
and a p
+
gate electrode
16
b
are formed.
Afterwards, the n
+
gate electrode
15
b,
the p
+
gate electrode
16
b,
and the exposed semiconductor substrate
10
are selectively oxidized to form a buffer insulating film
24
.
Subsequently, a mask process is respectively performed in the NMOS region I and the PMOS region II, so that a lightly doped impurity ion implants can be made into the NMOS region I and the PMOS region II. Thus, an n-LDD region
26
a
and a p-LDD region
26
b
are formed.
As shown in
FIG. 1C
, a double structure of an oxide film spacer
28
and a nitride film spacer
30
is formed at the sidewalls of the mask insulating film pattern
22
b,
the metal layer pattern
20
b,
the diffusion prevention film pattern
18
b,
and the n
+
gate electrode
15
b
the p
+
gate electrode
16
b
respectively.
Subsequently, a mask process is respectively performed in the NMOS region I and the PMOS region II, so that a heavily doped impurity ion is implanted into the NMOS region I and the PMOS region II. Thus, an n
+
source/drain region
27
a
and a p
+
source/drain region
27
b
are formed. The nitride film spacer
30
will act as an etching barrier in a later self-aligned contact process.
Afterwards, an interlayer insulating film
32
is formed on the upper portion of the entire surface and then planarized.
The aforementioned related art method for fabricating a semiconductor device has several problems.
The metal layer pattern constituting the gate electrode expands during later annealing processes. The metal layer pattern also expands due to etching selectivity differences between the mask insulating film and the metal layer pattern during etching process for forming the gate electrode. For this reason, the impurity ion is not implanted into a corner portion of the gate electrode during the subsequent ion implantation process for forming the LDD regions. Furthermore, lifting of the gate electrode can occur due to oxidation of the metal layer pattern. This deteriorates the device characteristics, yield and reliability.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method for fabricating a semiconductor device that substantially overcomes one or more of the problems limitations and disadvantages of the prior.
An object of the present invention is to provide a method for fabricating a semiconductor device which prevents a metal layer from being oxidized during subsequent high temperature processes such as an ion implantation process, by forming a conductive layer pattern of polysilicon or amorphous silicon in a gate electrode shape, forming an insulating film spacer at the sidewalls of the conductive layer pattern, forming an LDD region by a lightly doped impurity ion implantation, removing a predetermined thickness of the conductive layer pattern to form a metal layer pattern, and then forming a gate electrode.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a method for fabricating a semiconductor device according to the present invention includes the steps of: forming a gate insulating film on a semiconductor substrate provided with a cell region and a peripheral circuit region where NMOS and PMOS regions will be formed; forming an undoped polysilicon layer pattern having a gate electrode shape on the gate insulating film; forming an oxide film having a predetermined thickness on an upper portion of the entire surface; respectively forming an LDD region in the semiconductor substrate at both sides of the undoped polysilicon layer pattern of both in PMOS region in the peripheral circuit region and the NMOS regions in the cell region and the peripheral circuit region; forming a nitride film having a predetermined thickness on the upper portion of the entire surface; etching the nitride film and the oxide film without patterning to form a spacer having a double structure of a nitride film and an oxide film at sidewalls of the undoped polysilicon layer pattern; respectively implanting a heavily doped impurity ion into both spacers of the NMOS region and the PMOS region in the peripheral circuit region to form a source/drain region; forming an interlayer insulating film on the upper portion of the entire surface and then planarizing the interlayer insulating film to expose the undoped polysilicon layer pattern; removing a portion of the exposed undoped polysilicon layer pattern by the entire etching process to leave a predetermined thickness and form

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