Data processing: measuring – calibrating – or testing – Calibration or correction system
Reexamination Certificate
1998-10-09
2001-12-04
Assouad, Patrick (Department: 2857)
Data processing: measuring, calibrating, or testing
Calibration or correction system
C324S601000
Reexamination Certificate
active
06327545
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to circuit board testing. More particularly, this invention relates to the identification of manufacturing defects and faulty components on a circuit board.
BACKGROUND OF THE INVENTION
Generally, a circuit board consists of numerous interconnected components such as semiconductor chips, resistors, capacitors, inductors, etc. After circuit boards have been assembled, but before they can be used or placed into assembled products, they must be tested. Testing verifies that the proper components have been used, that each component performs within test limits, that all required electrical connections have been properly completed, and that all necessary electrical components have been attached to the board in the proper position and with the proper orientation. When a component is not performing within test limits, it is said to be faulty.
A common way to test assembled printed circuit boards is called in-circuit test. In-circuit testing involves probing individual board components through a so-called “bed-of-nails” and verifying their existence and specifications independent of surrounding circuitry. A well known series of circuit board testing machines for in-circuit testing is the Hewlett-Packard Company Model HP-3070 Family of Circuit Board Testers. The HP-3070 Family of board testers are fully described in the HP-3070 Family Operating and Service Manuals available from Hewlett-Packard Company. Other families of circuit board testing machines made by Hewlett-Packard are the HP-3060 and HP-3065 series.
To test each individual board component, in-circuit testing requires access to every node on the circuit board. With through-hole parts, access is directly available at component leads. With surface mount parts, access is provided through vias and test pads that are placed on the circuit board when it is designed. Increases in board density, however, have led to a decrease in the size of vias that has eclipsed the ability of probe technology to contact a smaller target. Vias now are often one hundred times smaller in area than vias used just a few years ago. Furthermore, test pads that are large enough to be probed successfully require a substantial amount of board area that would otherwise be used to place and connect components. Therefore, on many circuit boards it is no longer practical, or desirable, to probe every node on the board.
Accordingly, there is a need in the art for a test technique and apparatus that can test individual circuit board components having tolerances without requiring access to every node on the circuit board. Such a technique should be generalized so that it can be used with many different circuits and tolerance ranges. Furthermore, it is desirable that such a system be implemented on existing in-circuit testing hardware to preserve existing capital and process investments in that hardware.
SUMMARY OF THE INVENTION
In a preferred embodiment, the invention provides a correction of voltage measurements on a board with inaccessible nodes for parasitic effects of tester hardware. This correction allows a model of the circuit board without tester parasitics to be used to generate diagnostic matrices, limits, and patterns. These diagnostic matrices, limits, and patterns can then be used without modification with the corrected voltage measurements. The invention is generally applicable to all kinds of circuits, includes the ability to handle component tolerances, and may be implemented using existing computer and tester hardware.
The invention takes measurements on the board being tested and corrects these measurements for the parasitic effects of the detector and the stimulus source. A correction factor is then applied to this result to produce a set of corrected voltage measurements that can be used with the diagnostic matrices, limits, and patterns to check for faults. The correction factor is produced from a model of the circuit that includes some measured parasitics and some calculated parasitics and relates the voltages from a model without these parasitics to one with parasitics.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
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Ahrikencheikh Cherif
Browen Rodney A.
Darbie William P.
McDermid John E.
Agilent Technologie,s Inc.
Assouad Patrick
Neudeck Alexander J.
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