Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
1999-06-02
2001-11-27
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S298000, C257S301000, C257S304000, C438S629000, C438S672000, C438S675000
Reexamination Certificate
active
06323558
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a contact of a semiconductor memory device.
2. Description of the Related Art
FIGS. 1A-1B
sequentially illustrate a conventional method for fabricating a storage node of a semiconductor memory device. A conventional method for fabricating a storage node of a DRAM (dynamic random access memory) cell capacitor includes the following steps, as shown in FIG.
1
A. An interlayer insulation film
2
is formed on a semiconductor substrate
1
. The interlayer insulation film
2
is etched until an upper surface of a portion of the semiconductor substrate
1
is exposed, so that contact holes
3
, that is, storage node contact holes
3
, are formed. A conductive layer
4
for forming a storage node, for example, a polysilicon layer, is formed on the interlayer insulation film
2
so as to fill up the contact holes
3
.
The polysilicon layer
4
is patterned, as shown in
FIG. 1B
, by using a storage node formation mask (not shown). In this way, storage nodes
4
a
are formed.
FIG. 2
is a plan projection view showing the storage nodes
4
a
to be correctly aligned with the contact holes
3
.
If a misalignment between a storage node
4
b
and a contact hole
3
is generated in a storage node patterning process, as shown in
FIG. 3
, necking (reference numeral
5
) can occur. Necking occurs when a storage node
4
b
is narrowed by an overetch process which is conventionally performed during a dry etch process for patterning a storage node.
FIG. 4
is a plan projection view of FIG.
3
. Reference numeral
5
is a connecting section between the storage node
4
b
and the contact hole
3
. If the level of necking is too high or severe, the storage node
4
b
can fall down or fall off.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.
According to an aspect of the present invention, a semiconductor memory device comprises a semiconductor layer; an interlayer insulation film on the semiconductor layer; a contact hole in the interlayer insulation film, the contact hole penetrating through the interlayer insulation film down to the semiconductor layer; a first material filling a portion of the contact hole; and a contact electrode, including a conductive material, on a portion of the first material, wherein the first material has an etch selectivity with respect to the contact electrode.
According to another aspect of the present invention, a semiconductor memory device comprises a semiconductor substrate; an interlayer insulation film on the semiconductor substrate; a contact hole in the interlayer insulation film, the contact hole penetrating through the interlayer insulation film down to the semiconductor substrate; a contact plug in the contact hole and electrically connected to the semiconductor substrate, the contact plug having an upper surface lower than that of the interlayer insulation film; a first conductive layer covering the upper surface of the contact plug and a sidewall of the contact hole; a material layer pattern inside the contact hole surrounded by the first conductive layer; and a second conductive layer on a portion of the first conductive layer and the material layer.
REFERENCES:
patent: 5744389 (1998-04-01), Kim
patent: 5886411 (1999-03-01), Kohyama
Chaudhuri Olik
Peralta Ginette
Samsung Electronics Co,. Ltd.
The Law Offices of Eugene M. Lee, PLLC
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