Semiconductor integrated circuit device

Details Semiconductor integrated circuit device Semiconductor integrated circuit device

1999-08-12

2001-12-04

Clark, Sheila V. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S776000, C257S210000, C257S208000, C257S691000

Reexamination Certificate

active

06326693

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a standard cell or an embedded array.
2. Related Art
Semiconductor devices have been widely used in various fields of household electric appliances and developments of semiconductor integrated circuits for specific appliances have been strongly demanded. For this purpose, in recent years, an ASIC (Application Specific Integrated Circuit) technology has intensively been developed.
In the ASIC technology, two types of technology are employed, one is a standard cell system and the other is an embedded array system. The standard cell system has features of a high degree of integration and flexibility in design, and the embedded array system has a feature of a short development term in addition to the features of the standard cell system.
In either of the systems, in order to obtain higher integration, it is necessary to decrease area of interconnections while maintaining the flexibility in design.
There have been used two major methods for connecting a power terminal and a ground terminal to a semiconductor integrated circuit having a plurality of cores of ROMs and/or RAMs, etc.
These conventional connection methods will be explained in the following description with reference to
FIGS. 1-5
. It is to be noted that hereinafter the same parts will be indicated by the same reference numerals and their repeating explanations will be omitted.
The first method is a direct connection of the power and ground terminals to I/O cells of a core.
FIG. 1
is a plan view showing this method. As shown in
FIG. 1
, power terminals
101
a
,
101
b
,
102
a
and
102
b
connected to an I/O cell in a core
1
are provided at peripheral sides of the core
1
, and V
DD
and V
SS
are supplied to the power terminals. In this method, however, flexibility in design will be remarkably decreased since locations of the power terminals are fixed.
The second method is to dispose two interconnecting conductors in the peripheral part of the core to surround the core, with each of the conductors being connected to V
DD
and V
SS
.
FIG. 2
is a plan view for explanation of this method. Such configuration of the interconnections will be referred to “ring-shaped” hereinafter. Referring to
FIG. 2
, there are provided a first surrounding interconnection
111
around the core
1
and a second surrounding interconnection
112
around the first surrounding interconnection
111
. V
DD
and V
SS
are supplied to these interconnections
111
and
112
, respectively. The interconnections
111
and
112
are formed in the same layer, and for example, the interconnection
111
is connected to the core
1
via a coupling conductor (not shown in
FIG. 2
) formed in the same layer and lower layer and the interconnection
112
is connected to the core
1
via a coupling conductor formed in upper layer or lower layer. Thus by using ring-shaped interconnections, connections of power supply V
DD
and V
SS
to interconnections can be performed at any side, which results in improved flexibility in design.
This second method indeed improves flexibility in design when compared to the first method shown in
FIG. 1
, however, the second method requires additional area for arranging interconnections
111
and
112
which decreases the degree of integration. Since in the ASIC technology, a chip generally includes a plurality of cores, which require additional area for connections with power supplies of the plurality of cores, and therefore the integration of the whole device is remarkably decreased.
FIG. 3
shows a plan view of the semiconductor integrated circuit device
120
having two cores, to which the method shown in
FIG. 2
is applied. As shown in
FIG. 3
, two cores
1
and
2
are respectively provided with interconnections
111
surrounding each core and the interconnections
112
surrounding the interconnections
111
, respectively. This arrangement needs an area for
4
interconnections between the core
1
and the core
2
, which results in decrease in integration of the semiconductor device.
Furthermore, as shown in
FIG. 4
, in the case where a semiconductor integrated circuit device
140
has three or more cores (cores
1
,
2
and
3
) arranged in matrix form, areas for interconnections are necessary between neighboring cores in both x-direction and y-direction, which will remarkably decrease the integration of the device.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor integrated circuit having interconnections for supplying power in small area without deteriorating flexibility in design.
According to the first aspect of the invention, there is provided; a semiconductor integrated circuit device comprising; a core circuit having a plan rectangular shape, a first interconnection disposed around the core circuit and adapted to connect the core circuit to a first external terminal, and,
a second interconnection disposed around said first interconnection and adapted to connect the core circuit to a second external terminal, wherein said first interconnection and said second interconnection have overlapping parts formed through different layers.
It is preferable that said first interconnection has a plurality of layers for interconnection and said second interconnection has a plurality of layers.
X-direction portions of the first and the second interconnections are preferably formed in a first layer for interconnection, and, y-direction portions of the first and the second interconnections are preferably formed in a second layer for interconnection, both interconnections being in different levels.
According to the second aspect of the present invention there is provided;
a semiconductor integrated circuit device comprising; a plurality of core circuits each having a plan rectangular shape,a first interconnection disposed around the core circuit and adapted to connect the core circuit to a first external terminal, and, a second interconnection disposed around said first interconnection and adapted to connect the core circuit to a second external terminal,
wherein said first interconnection and said second interconnection have overlapping parts formed through different layers, and said first interconnection and said second interconnection use at least one side line between two adjacent core circuits commonly.
According to the third aspect of the present invention there is provided a semiconductor integrated circuit device comprising a core circuit having a plan rectangular shape, a first interconnection disposed around the core circuit and adapted to connect the core circuit to a first external terminal, a second interconnection disposed around said first interconnection and adapted to connect the core circuit to a second external terminal, and a logic circuit adjacent to said core circuit, wherein said first interconnection and said second interconnection have overlapping parts formed through different layers and parts of these interconnections located between the core circuit and the logic circuit being commonly used by the logic circuit and the core circuit.


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