Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2000-05-15
2001-11-27
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S150000, C438S151000, C438S479000, C438S482000, C438S486000, C148SDIG001
Reexamination Certificate
active
06323072
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor devices, and more particularly to semiconductor devices having a semiconductive thin film as its active layer and the manufacturing method thereof. The invention also relates to thin film semiconductor transistors with an active layer made of crystalline silicon films.
2. Description of the Prior Art
In the recent years semiconductor thin-film transistor (TFT) devices are becoming more widely used in the manufacture of electronic parts or components, particularly reduced-thickness display devices and digital integrated circuit (IC) packages, as the speed and cost advantages of these devices increase. As such electronics require higher packing density, higher speed, and lower power dissipation, TFTs become more critical in performance and reliability. Some prior known TFTs come with a silicon thin film as formed on a substrate with a dielectric surface, which film may typically measure several tens to several hundreds nanometers (nm) in thickness.
One typical TFT structure includes an active region as defined between spaced-apart source and drain regions for selective formation of a channel region therein. The active region, namely, the channel formation region and its associated source/drain junction regions may play an important role to determine the performance of TFT as a whole. This can be said because the resistance of a current path from the source to drain through the channel—i.e., the mobility of minority carriers—can strictly reflect the overall electrical characteristics of TFTs.
Conventionally, amorphous silicon films have been generally employed as the semiconductor thin film constituting the active layer of TFTs. These amorphous silicon films may be fabricated by plasma chemical vapor deposition (CVD) and low pressure thermal CVD techniques.
Unfortunately, the use of such amorphous films is encountered with a problem that where TFTs are required to exhibit higher speeds in operation, amorphous films are incapable of tracing such trend due to its inherently lowered mobility of charge carriers. To this end, silicon thin films with enhanced crystallinity (to be referred to as the “crystalline silicon film” hereinafter) should be required.
One example is that liquid crystal display (LCD) devices of the active-matrix type or passive type come with peripheral circuitry which requires use of driver circuits for driving picture elements or “pixels” each incorporating TFTs, controller circuits for treating image or video signals to be displayed, data storage circuits for storing several kinds of information, and others.
It is especially required that the controllers and storage circuits be equivalent in performance to integrated circuits (ICs) using known single-crystalline silicon wafers. Accordingly, where these circuits are integrated by use of thin film semiconductor as formed on a substrate, it is strictly required to fabricate on the substrate a crystalline silicon film that is identical in crystallinity to the single-crystalline materials.
One prior known approach to form such crystalline silicon film on the substrate has been disclosed, for example, in Published Unexamined Japanese Patent Application (PUJPA) No.6-232059 to be assigned to the present assignee. In this prior art a chosen metallic element or elements are employed to facilitate or accelerate crystal growth of silicon, which is subject to thermal or heat treatment at a temperature of 550° C. for four hours. With this, resultant crystalline silicon film offers enhanced crystallinity. A similar approach has also been disclosed in PUJPA No. 6-244103.
Unfortunately, even when the above technique is applied to the manufacture of an active layer of TFTs, resultant TFTs for use in processor circuits or memory circuitry remain insufficient in crystallinity. As the semiconductor manufacturers are commercially demanded to improve the TFT speed endlessly, employing the above prior art approach to provide the TFT active layer will be unable to catch up the strict demands due to their inherent limitations as to improvements of the crystallinity.
Especially, in order to achieve the crystalline silicon film having excellent crystallinity identical to that of single-crystalline materials, it should be required that substantially no crystal grain boundaries be present therein. This is because of the fact that the presence or inclusion of such crystal boundaries badly behaves as an energy barrier which can disturb movement or progress of electrons between adjacent crystal grains.
The mechanism of crystal growth by use of the above technique will be analyzed by subdividing the process thereof into four steps in connection with
FIGS. 10A
to
10
F.
See
FIG. 10A. A
silicon oxide film
11
is formed on the surface of a substrate as a buffer layer. An amorphous silicon film
13
is formed overlying the silicon oxide film
11
. Oxide film
11
has a configuration
12
on its surface, which has been formed due to the inherent surface roughness and/or presence of contaminants. The surface configuration
12
is depicted here as local projections for purposes of explanation only. The amorphous silicon film
13
is provided with a few of drops of coating solution containing a metallic element(s) for acceleration or facilitation of crystallization, and then rotated with circular rotational speed sufficient to centrifugally spin the coating solution uniformly and radially across the upper surface of film
13
. A coat layer
14
is thus deposited covering the upper surface of amorphous silicon film
13
as shown in FIG.
10
A. Coat layer
14
may contain nickel (Ni) as retained therein.
The structure of
FIG. 10A
is heated up to a temperature of from 500 to 700° C. for crystallization of amorphous silicon film
13
. Thus, the metallic element tends to internally diffuse isotropically within amorphous silicon film
13
as designated by arrows shown in
FIG. 10B
, finally reaching the interface between films
11
,
13
. This is the first of the prescribed four steps for analysis.
As a result of such internal diffusion, the metallic element migrates through the interface between films
11
,
13
leading to segregation on the local projections of surface configuration
12
as shown in FIG.
10
C. This is the second step. Such segregation occurs due to the fact that the metallic element attempts in nature to require stable cite of energy—in this case, the surface projections
12
act as such segregation cite.
At this time the surface projections
12
serving as the segregation cite contain one or several metallic elements at an increased concentration permitting occurrence of a crystal nucleus therein. Our study reveals the fact that where the metallic element is nickel, the crystal nucleus takes place when the concentration thereof is equal to or greater than 1×10
20
atoms per cubic centimeter. Crystal growth occurs with the crystal nucleus being as a starting point or “seed.” Such growth begins with vertical crystallization substantially perpendicular to the silicon film surface as shown by numeral
15
in FIG.
10
D. This is the third step.
The vertical crystal growth regions
15
of
FIG. 10D
is such that crystallization progresses while pushing upward the highly condensed metallic element(s) contained therein; accordingly, these elements are forced to reside in the surface of the overlying amorphous silicon film
13
at an increased concentration. This results in that vertical growth regions
15
remain greater in concentration of metallic element than the remaining regions of film
13
.
Then, as shown in
FIG. 10E
, crystal growth starts in a specific direction substantially parallel to the substrate surface (as designated by arrows shown) with a respective interface
16
between the amorphous silicon film
13
and the individual vertical growth region
15
being as a seed of crystallization. This results in lateral growth of crystals
17
, which is the fourth step. Each lateral crystal
17
may be a mixture of
Fukunaga Takeshi
Komaya Jun
Miyanaga Akiharu
Yamazaki Shunpei
Fish & Richardson P.C.
Lytle Craig P.
Semiconductor Energy Laboratory Co,. Ltd.
Smith Matthew
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