Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
1999-11-04
2001-02-06
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S037000, C326S082000, C326S016000, C714S726000
Reexamination Certificate
active
06184708
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit for selecting the slew rates of output buffers in an integrated circuit device. More specifically, the present invention relates to a circuit for automatically selecting the slew rates of output buffers in a programmable logic device attached to a populated printed circuit board, such that the output buffers experience a selected amount of signal reflection.
2. Related Art
Digital integrated circuits (ICs) are typically mounted on a printed circuit board, thereby enabling these ICs to be coupled to other integrated circuits, which are also mounted on the printed circuit board. When the digital ICs drive signals out onto the printed circuit board, signal reflections may occur as a result of the impedances of the printed circuit board traces and/or the impedances of other ICs mounted on the printed circuit board. In general, signal reflection occurs when an output signal is driven from a source pin onto a signal path having a relatively low impedance. The low impedance results in the output signal reflecting from the intended destination back to the source pin. If the source pin is an input/output (I/O) pin which receives input signals in addition to providing output signals, the reflected signal may be erroneously interpreted to be a valid input signal.
Early determination of signal reflections on a printed circuit board is critical to successfully debug today's high-speed circuits. Finding unwanted signal reflections is one of the single most difficult tasks to accomplish and frequently results in printed circuit board re-design to eliminate undesired signal reflections.
Time domain reflectometry (TDR) is a conventional technique used to determine passive impedance by using voltage pulses and timing measurements (similar to the manner in which radar devices determine distance). Printed circuit board manufacturers often use TDR to determine the impedance of printed circuit board traces. System designers typically use this impedance information to determine the time delay of signals that are driven onto the printed circuit board. When known, this impedance information helps to determine signal behavior on the printed circuit board, and enables the signal behavior to be improved if necessary. However, the impedances of the printed circuit board traces are measured before there are any devices mounted on the printed circuit board. The presence of devices mounted on the printed circuit board can change the effective impedances of the printed circuit board traces. Sophisticated circuit simulators have been used to model the behavior of devices attached to printed circuit boards with well-known circuit parameters. However, this modeling is difficult and frequently inaccurate.
It would therefore be desirable to have a system which determines the presence of signal reflections on a populated printed circuit board, and automatically eliminates or adjusts detected signal reflections.
SUMMARY
Accordingly, the present invention provides a system which includes a programmable logic device mounted on a populated printed circuit board, and a configuration processor. The programmable logic device includes a plurality of input/output blocks (IOBs), each having an input buffer and an output buffer. Each of the output buffers has an adjustable slew rate control circuit which is programmable to control the slew rate of the associated output buffer. Each of the input buffers can be selectively coupled to an asynchronous latch. Each of the output buffers can be selectively coupled to an adjustable delay line in the programmable logic device. The adjustable delay line is capable of generating digital pulses of different widths.
The configuration processor controls the programmable logic device to select the final slew rates for the various output buffers. The final slew rates are usually selected such that reflected signals are eliminated or minimized. The configuration processor controls each of the slew rate control circuits to provide a first slew rate. In one embodiment, the first slew rate is the fastest selectable slew rate. The configuration processor further controls the programmable logic device to couple each of the input buffers to its associated asynchronous latch, and each of the output buffers to the adjustable delay line. The configuration processor then controls the adjustable delay line to generate a first digital test pulse having a first width. In one embodiment, the first test pulse has a maximum width.
The first test pulse is applied to each of the output buffers, such that the test pulse is transmitted from each output buffer to the printed circuit board. The first test pulse can be applied to the output buffers simultaneously or sequentially. Depending on the impedances of the printed circuit board, the first test pulse transmitted from a particular output buffer may be reflected, thereby resulting in a reflected test pulse. The reflected test pulse returns to the associated input buffer. If the reflected test pulse has a sufficient magnitude, the input buffer transmits a signal to the associated asynchronous latch. In response, the asynchronous latch stores a value indicating the presence of the reflected test pulse.
By monitoring the asynchronous latches, the configuration processor determines which IOBs received a reflected test pulse, and which IOBs did not receive a reflected test pulse. In one embodiment, the contents of the asynchronous latches are transferred to JTAG boundary scan registers associated with the IOBs, and then shifted from these JTAG registers out of the programmable logic device. In response, the configuration processor adjusts the slew rate of the output signal from each IOB that received a reflected test pulse. In one embodiment in which it is desired to have no reflection, the slew rate is adjusted by selecting a slower slew rate. The first test pulse is again applied to the subset of the output buffers having the adjusted slew rates. Again, the associated input buffers and asynchronous latches detect and record any reflected test pulses.
This process is continued until there are no reflected test pulses, or until all the possible slew rates have been tested. If all of the slew rates have been tested, and there are still reflected test pulses, then the first test pulse can be replaced with a second test pulse having a different pulse width. In one embodiment, the second test pulse has a smaller width than the first test pulse. The slew rate testing then proceeds using the second test pulse and the various slew rates.
When no reflected test pulses are detected, the configuration processor transfers the final slew rates from the slew rate control circuits to associated JTAG registers of the programmable logic device. The final slew rates are shifted from the JTAG registers to the configuration processor, During the normal configuration of the programmable logic device, the configuration processor programs the slew rate control circuits with the final slew rates, thereby optimizing performance of the programmable logic device.
The present invention enables the automatic detection and elimination of reflected signals in a programmable logic device which has been mounted on a populated printed circuit board. The invention also enables the adjustment of reflection of signals where it is desirable to have a certain amount of reflection. Advantageously, the present invention reuses standard circuitry which is already present on the programmable logic device, including the adjustable delay line and the JTAG registers.
The present invention will be more fully understood in view of the following description and drawings.
REFERENCES:
patent: 5017813 (1991-05-01), Galbraith et al.
patent: 5144166 (1992-09-01), Camarota et al.
patent: 5331220 (1994-07-01), Pierce et al.
patent: 5644496 (1997-07-01), Agrawal et al.
patent: 5740410 (1998-04-01), McDermott
“The Programmable Logic Data Book”, 1996, available from Xilinx, Inc., 2100 Logic Drive, San Jose, California
Hoffman E. Eric
Paik Steven S.
Tokar Michael
Xilinx , Inc.
Young Edel M.
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