Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1998-10-07
2001-12-25
Nguyen, Vinh P. (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
Reexamination Certificate
active
06333636
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor wafer aligning system and method. More particularly, the present invention relates to a semiconductor wafer aligning system and method wherein a wafer floats on a fluid as the wafer is contacted by guides.
DESCRIPTION OF THE RELATED ART
Generally, in the semiconductor device fabrication process, wafers are processed in processing equipment after being moved by a transfer system for loading wafers, and then the wafers are moved to other processing equipment by a transfer system for unloading wafers.
A wafer aligning system is used to secure the wafer at a correct loading location on a stage of the processing equipment so that it may be moved within the processing equipment. If the wafer is not precisely aligned, the wafer may collide with fabrication equipment and may be broken, representing a malfunction of the wafer transfer system.
Generally, the aligning system for wafers can have various configurations and operating principles. Aligning systems can be divided into two different types, a wafer holding aligning system and a wafer guide aligning system. The first type holds the wafer securely by its edges and then moves it into alignment. The second type moves the wafer in contact with guides until alignment is achieved, and then holds the wafer securely by its edges.
The wafer holding aligning system and the wafer guide aligning system are normally operated such that the front surface of the wafer, which has a pattern thereon, faces upwardly and the back surface of the wafer faces downwardly, toward the aligning system.
While the wafer is aligned, any scratch occurring on the back surface of the wafer in contact with the system causes no direct difficulties. However, cleanliness of the cleanroom for semiconductor devices fabrication environment is important, and the ultrafine particles generated due to the scratches can affect the production yield and the reliability of the semiconductor device fabrication process.
In a wafer grinding process, the thickness of the wafer is reduced and the particles accumulated on the back side of the wafer are removed. During this process the back side of the wafer faces upwardly and the front side of the wafer, covered with tape, faces downwardly on the aligning system. Since the tape-covered front side of the wafer contacts the guide, any damage from the guide may penetrate the tape and cause scratches and direct damage to the front side.
In addition, to minimize damage from conventional alignment systems, the aligning operation is typically performed only one time. This makes it difficult to maintain a precise alignment throughout processing.
SUMMARY OF THE INVENTION
The present invention is directed to provide a semiconductor wafer aligning system for aligning a wafer precisely without causing wafer damage or generation of particles.
It is another object of the present invention to use a fluid on which the wafer is made to float to prevent damage and generation of particles.
Another object of the present invention is to provide a semiconductor wafer aligning method using the semiconductor wafer aligning system of the present invention while minimizing the amount of fluid usage.
To achieve these and other advantages and in accordance with the purpose of the present invention as embodied and broadly described, a semiconductor wafer aligning system includes a table having a spray opening for upwardly spraying ultrapure water to form a water surface on which a semiconductor wafer floats. A guide disposed on the table contacts the wafer at a circumferential edge, to guide the wafer into a correct location.
In another aspect of the present invention, an upward extended member is disposed on the table outside a peripheral edge of the spray opening such that the water surface is wider than the spray opening. It includes a wall having an open section such that the wafer floating on the water surface moves horizontally in a drift direction toward the open section.
In another aspect of the present invention, each of a left guide and a right guide of the guide includes a horizontal plate for supporting the bottom of the wafer when the wafer is not floating, and an upward protruded part connected to the horizontal plate for contacting the circumferential edge of the wafer. The protruded part is a screw protrusion having a male screw part. The horizontal plate has a plurality of female screws, each corresponding to a respective one of a plurality of wafer diameters.
In another aspect of the invention, a method of aligning a semiconductor wafer using the semiconductor wafer aligning system includes spraying ultrapure water. The spraying includes opening a valve leading to the spray opening so as to spray ultrapure water through the spray opening upward toward a wafer. The wafer is guided, after the spraying, by moving the wafer to a correct position with the guide, and then closing the valve so as to stop the spray of the ultrapure water.
By contacting and aligning a wafer which floats on a water surface of ultrapure water, the present invention substantially obviates one or more of the problems due to the limitations and disadvantages of the related art
REFERENCES:
patent: 3675563 (1972-07-01), Metreaud
patent: 4521995 (1985-06-01), Sekiya
patent: 4747589 (1988-05-01), Watson et al.
patent: 5421401 (1995-06-01), Sherstinsky et al.
patent: 5625433 (1997-04-01), Inada et al.
patent: 5689749 (1997-11-01), Tanaka et al.
patent: 5931465 (1999-08-01), Miyake et al.
Nguyen Vinh P.
Samsung Electronics Co,. Ltd.
Volentine & Francos, PLLC
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