Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-12-21
2001-10-30
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C257S316000
Reexamination Certificate
active
06310374
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device and, more particularly, to a nonvolatile semiconductor memory device which writes data by the self-boost write method.
Recently, a demand for nonvolatile semiconductor memory device has greatly increased because these memories have the advantages that, e.g., data is not erased even when the power supply is turned off. In a flash memory which is an electrically simultaneously erasable nonvolatile semiconductor memory device, the memory cell can be formed by one transistor unlike in a two-transistor type byte nonvolatile semiconductor memory device. As a consequence, the memory cell shrinks, so the possibility of use of this flash memory as, e.g., a substitute for a large-capacity magnetic disk and the like is being explored.
Among other flash memories, a NAND EEPROM is known as a memory particularly advantageous to increase the degree of integration. This memory has the following structure. That is, a plurality of memory cells are arrayed in the column direction, and the source and drain of each pair of adjacent cells are connected. This connection forms a unit cell group (NAND cell) in which a plurality of memory cells are connected in series. This unit cell group is connected as a unit to a bit line.
A memory cell has a stacked gate structure in which a floating gate which commonly functions as a charge storage layer and a control gate electrode are stacked. Such memory cells are integrated in a matrix manner in a p-type well which is formed in a p-type substrate or an n-type substrate. The drain side of the NAND cell is connected to a bit line via a selector gate. The source side of the NAND cell is connected to a source line (reference potential line) via a selector gate. The control gate of each memory cell is connected to a word line extending in the row direction.
Data is written in or erased from the NAND cell by injecting or releasing electrons into or from the floating gate of a memory cell. Data erase is performed as follows. For example, in a whole memory cell array, all word lines are set to 0V, and an erase voltage Vee of about 20V is applied to the substrate or well, thereby causing all memory cells to release electric charge from their floating gates to the substrate. Consequently, all memory cells are erased to a “1” data state in which the threshold value is negative. If a plurality of memory cell array blocks are present, data erase is sometimes performed in units of blocks. If this is the case, selected blocks are processed under the above conditions, and all word lines float in non-selected blocks.
Data write is performed in the following manner. A write voltage Vpp of about 20V is applied to a selected word line to which a memory cell in which data is to be written is connected. An intermediate voltage Vpass is applied to other non-selected word lines in the NAND cell. Also, the channel potential of the memory cell connected to the selected word line is controlled in accordance with whether the write data is “0” or “1”. That is, if the write data is “0”, 0V of the bit line is transferred to the channel of the memory cell to inject electrons into the floating gate by a tunnel current. Accordingly, the threshold value of the memory cell becomes positive. On the other hand, if the write data is “1”, the channel potential of the memory cell is set through the bit line to an intermediate potential by which no tunnel injection takes place. Consequently, the threshold value of the memory cell is kept low and negative.
Data read is performed by applying 0V to a selected word line and an intermediate voltage by which a memory cell is turned on to the rest of word lines in the NAND cell regardless of whether the data is “0” or “1”, and detecting through the bit line whether the NAND cell is turned on.
In writing data into a NAND EEPROM as described above, if low-voltage driving is realized a column peripheral circuit connected to a bit line can be constructed by Vcc transistors. This decreases the area of this peripheral circuit. In consideration of this advantage, the self-boost write method in which only the channel potential of a memory cell in which “1” data is to be written is sufficiently raised by using capacitive coupling has been proposed and put into practical use. A write performed by this self-boost write method will be described below.
FIG. 1
is an equivalent circuit diagram of a memory cell unit of a conventional NAND EEPROM. Reference symbols BL, SG, CG, and SL denote a bit line, selector gate line, word line, and source line, respectively.
If data write simultaneously performed for a plurality of memory cells in the row direction is a common write, data is sequentially written from the memory cell farthest from the bit line BL. If the data write is a random write, data is written in an arbitrary memory cell between the bit line BL and the source line SL.
In either case, 0V is applied to a selector gate line SG
2
near the source line SL to switch off a selector gate transistor. A bit line BL to which a NAND cell having a memory cell in which “0” data is to be written is connected is set to a write selection potential of 0V. A bit line BL to which a NAND cell having a memory cell in which “1” data is to be written is connected is set to a write non-selection potential, more specifically, a potential higher than that of a selector gate line SG
1
near the bit line BL or a potential which is lower than that of the selector gate line SG
1
but by which a selector gate transistor is cut off. Note that a predetermined positive voltage is supplied to the source line SL to sufficiently cut off a selector gate transistor near the source line SL.
When the write voltage Vpp or the intermediate voltage Vpass is applied to a word line CG of a selected block in this state, memory cells are turned on when the voltage pulse rises. As a consequence, 0V is transferred to the channel of the NAND cell connected to the bit line BL set at 0V as the write selection potential. Accordingly, electrons are injected by a tunnel current into the floating gate of a memory cell connected to a selected word line, and “0” data is written in the cell.
In the NAND cell connected to the bit line BL set at the write non-selection potential, an initial potential obtained by subtracting the threshold value of the selector gate transistor from the potential of the bit line BL is transferred to the channel of the NAND cell from the bit line BL via the selector gate transistor. After that, the selector gate transistor near the bit line is cut off to float the channel of the NAND cell. Therefore, when the write voltage Vpp or the intermediate voltage Vpass is applied to the word line CG of the selected block, the capacitive coupling between these word line and NAND cell channel boots the channel potential of the NAND cell from the initial potential as described above. Consequently, the floating gate of a memory cell connected to a selected word line is also set to a write inhibit voltage by which no tunnel injection occurs. That is, “1” data by which the threshold value of the memory cell is kept negative is written.
A write inhibit voltage actually obtained by the self-boost write method is calculated below by taking account of the write timings in this method. Assume that the potential of the bit line BL is set to 0V or a power-supply voltage Vcc (e.g., 3.3V) in accordance with write data, Vcc is supplied to the source line SL and the selector gate line SG
1
near the bit line BL, and 0V is supplied to the selector gate line SG
2
near the source line SL. If the write voltage Vpp (e.g., 20V) and the intermediate voltage Vpass (e.g., 10V) are applied to a selected word line CG and a non-selected word line, respectively, of a selected block, the floating channel of the NAND cell is booted to a write inhibit voltage Vch. This write inhibit voltage Vch is represented by
Vch=Vsg−Vsgth
(
Vchinit
)+
Cr
1
(
Vpass−Vpassth
(
Vchinit
))+
Cr
2
(
Vpp−Vpassth
Aritome Seiichi
Satoh Shinji
Shirota Riichiro
Chaudhuri Olik
Hogan & Hartson L.L.P.
Kabushiki Kaisha Toshiba
Pham Hoai
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