Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1997-12-10
2001-02-20
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S355000, C257S363000
Reexamination Certificate
active
06191454
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a CMOS (Complementary Metal-Oxide Semiconductor) structure and, more particularly, to a semiconductor device having a protective resistance element serving as an input/output protection circuit.
A conventional semiconductor device has a protective resistance element arranged between an input terminal and an internal circuit to protect the internal circuit.
FIG. 3
shows such a conventional semiconductor device. Referring to
FIG. 3
, a p-type well
5
is formed in the surface of a p
−
-type silicon substrate
1
having a flat major surface
3
. A transistor
52
having an n-channel MOS structure is formed in the p-type well
5
. A first n-type well
4
is formed to be separated from the p-type well
5
by an isolation region, and a transistor
51
having a p-channel MOS structure is formed in the first n-type well
4
.
A second n-type well
6
is formed adjacent to the p-type well
5
. The second n-type well
6
serves as the diffusion layer of a protective resistance element
53
serving as a protection circuit. The respective regions are partitioned by a silicon oxide film
2
which is selectively formed on the substrate
1
by using selective oxidation, e.g., LOCOS (LOCal Oxidation of Silicon). The silicon oxide film
2
has a depth of, e.g., 400 nm, from the major surface
3
of the substrate
1
, and is formed to have a total thickness of 800 nm.
In the transistor
51
, a p
+
-type source
12
, a p
+
-type drain
13
, and an n
+
-type substrate contact region
11
are formed in the major surface
3
of the substrate
1
corresponding to the first n-type well
4
. A polysilicon gate electrode
22
is formed in a channel region
31
of the first n-type well
4
through a gate insulating film
21
having a thickness of 30 nm to 50 nm. A side wall
29
is formed to cover the two sides of the gate electrode
22
.
In the transistor
52
, an n
+
-type source
15
, an n
+
-type impurity region
16
as a drain, and a p
+
-type substrate contact region
14
are formed in the major surface
3
of the substrate
1
corresponding to the p-type well
5
. A polysilicon gate electrode
24
is formed on a channel region
32
of the p-type well
5
through a gate insulating film
23
having a thickness of 30 nm to 50 nm. Another side wall
29
is formed to cover the two sides of the gate electrode
24
.
In the protective resistance element
53
, the second n-type well
6
is formed by diffusion simultaneously with the first n-type well
4
. The n-type impurity concentration of the second n-type well
6
, which determines the resistance of the resistance element, in a surface region
33
is 1×10
15
cm
−3
. An n
+
-type impurity region
17
is formed in the major surface
3
of the,substrate
1
corresponding to the second n-type well
6
. The impurity region
16
formed in the p-type well
5
of the transistor
52
extends into the second n-type well
6
.
A polysilicon control electrode
26
is formed in the surface region
33
(channel), serving as a resistor against a current in the second n-type well
6
, through an insulating film
25
having a thickness of 10 nm to 70 nm. Still another side wall
29
is formed to cover the two sides of the control electrode
26
.
The source
12
, substrate contact region
11
, and gate electrode
22
of the transistor
51
, and the control electrode
26
of the protective resistance element
53
are connected to a power line
41
, and a positive voltage V
DD
as a high-potential power supply voltage is applied to them. The source
15
, substrate contact region
14
, and gate electrode
24
of the transistor
52
are connected to a ground potential V
GND
as a low-potential power supply voltage through a GND line
44
.
The impurity region
17
of the protective resistance element
53
and the drain
13
of the transistor
51
are connected between an input contact
42
and an output contact
43
which is connected to an internal circuit. That is, the protection circuit described above is connected to hang between an external input and the internal circuit.
With the above arrangement, when an abnormal voltage is externally applied, the protection circuit described above is set in a snap-back state to flow the abnormal voltage to the GND line
44
. When the snap-back state is effected before the gate insulating film of the transistor constituting the internal circuit causes breakdown, the internal circuit is protected.
The impurity region
16
as the drain and the n
+
-type source
15
of the transistor
52
are respectively connected to an n
−
-type region
16
′ and an n
−
type region
15
′ to form an LDD structure. Similarly, in the protective resistance element
53
, the impurity region
17
and the impurity region
16
are respectively connected to an n
−
-type region
17
′ and the n
−
type region
16
′ through a region under the control electrode
26
, thus forming an LDD structure.
These LDD structures smooth the impurity concentration gradient to moderate the electric field applied to them. The n
+
-type region and the n
+
-type source and drain are formed simultaneously, and their n-type surface impurity concentration is 5×10
20
cm
−3
. The surface impurity concentration of the n
−
-type region constituting the LDD is 1×10
17
cm
−3
.
By employing silicide formation, a silicide film
30
is formed by self alignment for achieving a high operation speed on the surface of each of the p
+
- and n
+
-type regions that form a prospective source and drain, by using the silicon oxide film
2
and the corresponding side wall
29
as the mask. Similarly, another silicide film
30
is formed by self alignment on the upper surface of each silicon gate electrode by using the corresponding side wall
29
as the mask.
This silicide formation has become necessary along with the recent increase in operation speed and micropatterning of the CMOS semiconductor device. According to the silicide formation technique, when a refractory metal film is formed on the surface of a silicon substrate including a source, a drain, and the like, and on the surface of a silicon gate electrode, and is annealed for achieving a higher operation speed for a MOS transistor, silicide thin films can be formed on these surfaces by self alignment to decrease their surface resistance.
As described above, since the protective resistance element
53
is formed on the substrate
1
, a signal input to the drain
16
of the transistor
52
passes through the protective resistance element
53
. As a result, a voltage drop occurs even if the signal input to the drain
16
is an abnormal voltage, so that a high-level abnormal voltage is prevented from being applied to the transistor
52
.
Since a gate electrode structure (control electrode
26
) is formed on the surface of the diffusion layer of the protective resistance element
53
, even if the silicide formation is employed, a silicide film is not formed in this surface region. An undesired decrease in resistance of the surface region can be avoided accordingly, so that a predetermined resistance large enough to decrease the peak value of the surge voltage can be obtained with a diffusion layer (second n-type well
6
) having a small area.
To avoid formation of a silicide film, an oxide film, which is thick like the element isolation region, may be formed. In this case, an extra area is needed because of a bird's beak formed on the end portion of the thick oxide film. Then, the oxide film extends by 0.5 &mgr;m on each side. In fact, however, since merely a thin gate insulating film having a thickness of about 10 nm to 70 nm is formed in the surface region of the diffusion layer of the protective resistance element
53
, this extra portion can be eliminated. As a result, a further increase in integration degree is enabled. Also, an inconvenience of carrier trapping caused by the disorder of cry
Hatta Toshiya
Hirata Morihisa
Terai Kouji
Foley & Lardner
Loke Steven
Nadav Ori
NEC Corporation
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