Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-01-08
2001-10-23
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06308310
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a system for avoiding electromigration in circuits, such as, LSI circuits.
BACKGROUND OF THE INVENTION
In general, computer aided design (CAD) is used for the circuit design of LSI. Application of CAD to the circuit design of LSI is discussed on pages 31 to 62 of a publication entitled “CAD FOR LOGIC DEVICES” issued Mar. 20, 1980 by Information Processing Society in Japan.
The trend in LSI technology has resulted in narrower interconnection lines and smaller contacts. This has aggravated the electromigration-induced failure problem.
Potential electromigration-induced failure exists in the conductors with narrow effective cross-sectional areas at portions which allow the passage of large current. Examples of such portions are conductor lines and contacts in circuit elements, power supply conductor lines, and signal conductor lines. In the description, “circuit element” is herein defined and used as a general term of all elements of logic circuits, such as flip-flops, gates, etc.
It is the conventional practice to manually correct potential electromigration-induced failures by modifying a wiring pattern after the layout of circuit elements or by elaborating circuit design to shorten a conductor line or via.
JP-A- 4-242959 discloses a semiconductor device that has regions reserved for possible expansion of width of each power supply line or via. Thus, without any substantial modification of the layout, the width of each power supply line or via can be increased in response to the result of a calculation of current density between a power source and ground.
JP-A 2-188943 discloses a system for laying power supply lines of LSI circuits. This system sets paths or routes along which power supply lines are laid after determining appropriate positions of circuit elements in accordance with a designed layout. Subsequently, the system determines the time average electric power consumed by each of regions separated by the power supply line routes. Based on the determined values of electric power, the system determines the effective time average values of electric current for the regions, respectively. Using the determined effective time average values of electric current and power supply resistance conductors connecting the regions to a power supply pad, the system determines electric current values of the power supply lines, respectively. In accordance with these results, the system determines the appropriate width of each of the power supply lines.
JP-A 4-365350 discloses a system for avoiding electromigration in power supply lines. The system inputs information as to electric power consumed by each of logic elements. Then, it determines an appropriate combination of logic elements within each range to which one of the power supply lines can supply electricity. In the process, the system selects one of the logic elements and evaluates whether the selected one element can be a new constituent of the combination. For evaluation of the selected logic element, the sum of values of the electric power consumed by the selected logic element and the current elements of the combination is compared with an upper limit of electric power that is allowed to be supplied to the range. The selected logic element becomes a new element of the combination when the sum of electric power is less than the upper limit. However, the selected logic element is not allowed to become the new element of the combination when the sum of electric power is not less than the upper limit. In this manner, the electric current density of each power supply line is limited, so that the width of each power supply line is left unaltered.
P. Yang et al., “Design for Reliability: The Major Challenge for VLSI,” Proceedings of the IEEE, vol. 81, No. 5, May 1993, pp. 730-744 discuss selected reliability issues within the context of the design-in reliability concept. In this paper, electromigration models and current density estimation issues are discussed (see pp. 731-732).
An object of the present invention is to provide a system that can automatically avoid potential electromigration-induced failure problem during design of LSI circuits.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, there is provided a system for avoiding electromigration-induced failure problem in an integrated circuit, which system is operative to determine electric current density of electric current that would pass through a conductor line lying along a first path, and to determine a position of a buffer for insertion into said first path when said determined electric current density is not less than a predetermined reference value.
According to another aspect of the present invention there is provided a method of avoiding electromigration-induced failure problem in an integrated circuit, comprising the steps of:
determining electric current density of electric current that would pass through a conductor line lying along a first path;
comparing said determined electric current density with a predetermined reference value; and
determining a position of a buffer for insertion into said first path in response to said comparing result.
According to still another aspect of the present invention, there is provided a system for avoiding electromigration-induced failure problem in an integrated circuit, which system is operative to find potential electromigration-induced failure problem along a conductor line lying along a first path, and to determine a position of a buffer for insertion into said first path upon finding the potential electromigration induced failure problem.
REFERENCES:
patent: 5317207 (1994-05-01), Mortensen
patent: 5978701 (1999-11-01), Johnson
patent: 2-188943 (1990-07-01), None
patent: 4-242959 (1992-08-01), None
patent: 4-365350 (1992-12-01), None
Article—“Design for Reliability: The Major Challenge for VLSI”, Ping Yang, Fellow, IEEE, and Jue-Hsien Chern, Member, IEEE (Proceedings of the IEEE, vol. 81, No. 5, May 1993).
Article—CAD for Logic Devices, Information Processing Society in Japan, Mar. 20, 1980, pp. 31-62.
Do Thuan
Foley & Lardner
NEC Corporation
Smith Matthew
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