Column for module component

Details Column for module component Column for module component

1995-12-07

2001-12-18

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Insulating material

C257S712000, C257S706000

Reexamination Certificate

active

06331731

ABSTRACT:

TECHNICAL FIELD
This invention generally relates to modules that include an integrated circuit chip therein. More particularly, the invention relates to a column in a module component, the column being capable of transferring heat or equalizing the density of a component surface to enhance uniformity of the etching of the surface.
BACKGROUND OF THE INVENTION
FIG. 1
illustrates a prior art module
10
that includes an integrated circuit chip
12
in a cavity
14
formed by a package
16
and a cap
18
. The module
10
is made by positioning solder (not shown) between the chip
12
and bond pads
20
of the package
16
. Upon exposure to elevated temperature, the solder collapses to form electrical connections
22
between the chip
12
and the package
16
and to bond the chip
12
and package
16
together. This method of connecting the chip
12
and the package
16
is referred to as the controlled collapse chip contact/connection (C4) method. A layer
24
of adhesive paste between the chip
12
and the cap
18
attaches the cap
18
to the chip
12
.
Heat generated when electricity passes through the chip
12
must be removed from the chip
12
to prevent its damage. The heat is generated on the side of the chip
12
where the connections
22
are made. Typically, heat is removed from a backside
26
of the chip
12
which requires the heat to be conducted through the chip
12
, the adhesive layer
24
and the cap
18
before it is dissipated away from the module
10
with the help of fin array
28
on the cap
18
. The fin array
28
is required because the cap
18
is not a large enough heat sink, i.e., the cap
18
cannot absorb large amounts of heat and release it quickly, to lower the temperature of the chip
12
. The adhesive layer
24
acts as a thermal insulator which slows the removal of heat from the chip
12
. Heat removal is also slowed because the heat must be transferred through the chip
12
and the cap
18
.
Heat is not removed through the package
16
because multiple thin layers
30
of insulator greatly inhibit the flow of heat therethrough. A substrate
31
of the package
16
is a much better heat sink than the cap
18
but the thin insulator layers
30
prevent its use as a heat sink.
The thin insulator layers
30
electrically insulate metal electric vias
32
which have a cross-sectional area effective to permit an electrical connection between the chip
12
and input/output pins
34
but ineffective to contribute to heat transfer through the insulator layers
30
. The cross-sectional dimension of the electrical vias
32
is less the line width specified by patterning ground rules.
Each layer
30
is conventionally formed by laying down a seed metal layer, laying down a layer of resist material, selectively removing the resist material to form holes and lines in locations where metal will be plated (for the vias
32
that provide electrical paths between layers and lines
36
that provide electrical paths on a layer, respectively), plating up a metal layer in the locations, removing the resist material, etching to remove the seed layer and depositing insulator (unless indicated otherwise, these layers are not shown). The total surface area of the vias
32
on one of the insulator layers
30
is extremely small and is typically less than about 0.1 percent based on the total surface area of the insulator layer
30
. Further, not all vias, e.g., via
32
A, extend through all of the insulator layers
30
. The extremely small surface area and the vias not extending through all of the insulator layers
30
contributes to the poor heat transfer through the insulator layers
30
and the layers
30
being thermal insulators. Within the insulator layers
30
are regions
38
with no vias or lines which causes the regions
38
to etch at a rate faster than the regions adjacent to the vias. The unequal etch rate causes over etching in the regions
38
; with the vias
32
in adjacent areas not being uniform but rather varying in cross-section and height. The unequal etch rate also results in the insulator layers
30
not being planar on a microscopic scale (which cannot be illustrated in FIG.
1
). When the insulator layers
30
are not planar, the vias
32
in adjacent insulator layers
30
may not align which results in the package
16
being defective. The problem of over etching and the insulator layers not being planar also occur in conventional lift off and subtractive metallization processes.
The lines
36
are only formed where they are needed to provide electrical connections and do not extend into regions
38
A where they are not needed for electrical connections.
The electrical vias
32
include signal vias
32
B that permit the chip
12
to communicate with other chips (not shown). The signal vias
32
B often exposed to each other which permits “cross-talk” therebetween that interferes with the communications. The vias
32
do not shield the signal vias
32
A to inhibit cross-talk.
FIG. 2
illustrates an alternative module
10
A wherein chip
12
A is electrically connected to a package
16
A using wires
50
that extend from the chip
12
A to wire bond pads
52
on the package
16
A; this technique is known as wire bonding. There are no thin insulator layers between the chip
12
A and a substrate
31
A of the package
16
A. Therefore, heat can be transferred from the chip
12
A through the substrate
31
A to cool the chip
12
A.
A component of a module that exhibits improved heat transfer capabilities or enhances the uniformity of the etching of a surface thereof and which does not exhibit the above shortcomings is highly desirable.
SUMMARY OF THE INVENTION
The invention provides a component for a module that is capable of receiving a chip therein that is connected by a controlled collapse chip contact/connection method. The component includes at least one column therethrough that is capable of transferring heat through the component or equalizing the density of a component surface to enhance uniformity of etching of the surface. The component is a thin insulator layer of a package or a cap.
Numerous other advantages and features of the present invention will become readily apparent from the following detailed description of the preferred embodiments and the appended claims.


REFERENCES:
patent: 4651192 (1987-03-01), Matsushita et al.
patent: 5099310 (1992-03-01), Osada et al.
patent: 5138439 (1992-08-01), Kobiki
patent: 5324987 (1994-06-01), Iacovangelo et al.
patent: 5506755 (1996-04-01), Miyagi et al.
patent: 5543661 (1996-08-01), Sumida
patent: 5-267512 (1993-10-01), None
IBM TDB vol. 31 No. 4 Sep. 1988, “Thermal Enhancement of Thermal Cap”, pp. 372-373.

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