Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-09-29
2001-02-13
Ray, Gopal C. (Department: 2781)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S120000, C710S120000, C710S008000, C370S402000
Reexamination Certificate
active
06189063
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates in general to the field of PCI to PCI bridge devices and more specifically to a method and apparatus for intelligent configuration register access on a PCI to PCI bridge.
BACKGROUND OF THE INVENTION
A peripheral component interconnect (PCI) bridge provides a connection path between two independent PCI buses. The primary function of a PCI to PCI bridge is to allow transactions to occur between a device on one PCI bus and a device on the other PCI bus. System and option card designers can use multiple PCI to PCI bridges to create an hierarchy of PCI buses. This allows system and option card designers to overcome electrical loading limits.
In a transaction between two PCI devices, the PCI device that initiates the transaction is called the master and the other PCI device is called the target. If the master and target are on different PCI buses, the bus that the master resides on is the initiating bus. The bus that the target resides on is the target bus.
A PCI to PCI bridge has two PCI interfaces, each connected to a PCI bus. The PCI interface of the PCI to PCI bridge that is connected to the PCI bus that is closest to the CPU is the primary interface. The PCI interface of the PCI to PCI bridge that is connected to the PCI bus that is farthest from the CPU is the secondary interface. Similarly, the PCI bus that is connected to the primary interface of the PCI to PCI bridge is called the primary PCI bus. The PCI bus that is connected to the secondary interface of the PCI to PCI bridge is called the secondary bus.
A PCI to PCI bridge acts essentially as an intermediary between devices located on the secondary bus and devices that are located on the primary bus. The two interfaces of the PCI to PCI bridge bus are capable of both master and target operations. The PCI to PCI bridge acts as a target on the initiating bus on behalf of the target that actually resides on the target bus. Similarly, the PCI to PCI bridge functions as a master on the target bus on behalf of the master that actually resides on the initiating bus. To devices located on the primary bus, the PCI to PCI bridge appears as one device where it actually represents several PCI devices that are located on the secondary bus. A detailed specification for PCI to PCI bridges is set forth in “PCI to PCI Bridge Architecture Specification”, Revision 1.0, Apr. 5, 1994, PCI Special Interest Group, Hillsboro, Oreg.
With respect to PCI devices connected to a PCI bus, the PCI specification requires dynamic data to be loaded in configuration space of a PCI device prior to device initialization. An example of such configuration data is the subsystem ID and subsystem vendor ID registers of a PCI device. This data is used to uniquely identify an add-in board or subsystem where the PCI device resides. The data needs to be populated prior to BIOS or other system software accessing the PCI configuration space of the PCI device. A typical implementation is to have a serial EEPROM for each PCI device in the subsystem. The configuration data is then loaded from the serial EEPROM prior to system software execution. Each PCI device in the subsystem also needs to guarantee that the data is valid before allowing reads to the registers to complete. In general, conventional PCI devices need to implement the required configuration registers and some sort of mechanism to load valid data into the registers.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method and apparatus for intelligent configuration register access on a PCI to PCI bridge are provided that substantially eliminate or reduce problems associated with previously developed PCI to PCI bridge devices.
The method and apparatus involve identifying a read to configuration information of a connected PCI device. It is then determined whether the connected PCI device is one for which the read should be trapped. If the read should not be trapped, the read is passed on to the connected PCI device. If the read should be trapped, the type of PCI device is determined for the connected PCI device. Data is then returned representing the configuration information in a format appropriate for the type of PCI device. In one aspect, the configuration information comprises the subsystem ID and subsystem vendor ID of the PCI device.
A technical advantage of the present invention is that a low-cost, intelligent scheme for configuration register access is provided that eliminates some overhead (e.g., cost, board area, complex design) for implementing and loading configuration registers. Further, there is no necessity for data storage, such as an EEPROM, to be associated with each PCI device in the subsystem.
Another technical advantage is that the PCI to PCI bridge device can handle configuration register access for older PCI devices that do not implement the required registers. Thus, such older PCI devices can work in newer systems that expect the configuration registers to be implemented.
Additional technical advantages should be readily apparent from the drawings, description, and claims.
REFERENCES:
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patent: 5913045 (1999-06-01), Gillespie et al.
patent: 5930496 (1999-07-01), MacLaren et al.
patent: 5968156 (1999-10-01), Kim
patent: 5983303 (1999-11-01), Sheafor et al.
Dickens David E.
Patel Krunali
Rekeita David W.
Brady III Wade James
Ray Gopal C.
Swayze, Jr. W. Daniel
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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