Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2000-06-02
2001-10-16
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S040000, C716S030000, C711S170000
Reexamination Certificate
active
06304101
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a programmable logic device suitable in the case where plural circuits are sequentially reconfigured to take on a part of processing by an application program for example. Particularly, the present invention relates to a method of reducing time required for reconfiguring a programmable logic device.
2. Description of the Related Art
In the field of a digital device, a programmable logic device such as a field programmable gate array (FPGA) and a programmable logic device (PLD) has been used for prototypical device before an application specific integrated circuit (ASIC) is produced or for a substitute device of ASIC that requires a long term for production from a few weeks to a few months. Also recently, a programmable logic device is used to change specifications after a device is produced and to enable modifying a circuit.
FIG. 22
shows the configuration of a programmable logic device in general. The programmable logic device
1
includes a circuit information input controller
2
for reading circuit information from an external device and a programmable logic circuit
3
for implementing a circuit function according to the read circuit information.
Further detailedly, the programmable logic circuit
3
includes a circuit element
4
and a configuration memory
5
connected to the circuit element
4
as shown in FIG.
23
. The circuit element
4
includes an input/output device, logic circuit cells and wiring. Depending upon the configuration of the connection of the circuit element
4
, the programmable logic device is classified into an FPGA type and a CPLD type.
In a programmable logic circuit
3
A of the FPGA type, logic circuit cells
6
A arrayed in the shape of a cross grating are mutually connected via wiring
7
A as shown in FIG.
24
A. Each logic circuit cell also receives a signal from a external device or outputs a signal to an external device via an input/output device
8
A connected to the respective four sides of the rectangular wiring
7
A when viewed as a whole.
Also, in a programmable logic circuit
3
B of the CPLD type, input/output devices
8
B and logic circuit cells
6
B are connected to wiring
7
B in tree structure as shown in FIG.
24
B.
In both structure, circuit information read in the programmable logic device
1
is written to the configuration memory
5
by the circuit information input controller
2
. According to the circuit information written to the configuration memory
5
, the function and the connected state of the circuit element are determined. This operation is called the reconfiguration of the programmable logic device or configuration.
[Description of reconfigurable computing technique]
Recently, in the field of reconfigurable computing to implement higher speed processing than software processing using a general purpose processor by hardware processing using a dedicated processing circuit for the processing of an application, a programmable logic device is starting to be utilized.
In reconfigurable computing, the circuit information of plural processing circuits required in the processing of an application is stored in an external storage beforehand and if necessary, a required circuit is implemented in a programmable logic device by writing the circuit information read from the external storage to the configuration memory of the programmable logic device.
The technique is called cache logic technique in view of saving required circuit information outside a programmable logic device and is called virtual logic technique in view of implementing a circuit larger in scale than the scale of an actual programmable logic circuit by rewriting circuit information. In the following description, these technologies are generically called cache logic technique for simplification.
The cache logic technique is time sharing driving technique that different circuits are configured in the same programmable logic device if necessary. As a result, circuits exceeding the scale of a programmable logic device can be implemented using the programmable logic device small in scale, the device can be miniaturized and the cost can be reduced.
However, there is a problem that depending upon the scale of circuit information written to the configuration memory of a programmable logic device, it takes much time to write circuit information from an external storage to the configuration memory of the programmable logic device and the whole processing time including circuit reconfiguring time is longer than software processing time even if high speed processing is implemented using a dedicated hardware processing circuit.
One solving method of the problem is device technique called multicontext technique. That is, in the multicontext technique, plural configuration memories are provided so that plural circuit information pieces can be stored in a programmable logic device and circuit reconfiguring time is greatly reduced by reconfiguring the programmable logic device by switching the configuration memories if necessary.
[Description of programmable logic device based upon multicontext technique]
FIG. 25
shows the structure of a programmable logic device base upon multicontext technique. The programmable logic device
10
based upon the multicontext technique includes a circuit information input controller
11
that reads plural circuit information pieces from an external device, a circuit information selection controller
12
that selects required circuit information out of plural circuit information pieces and a programmable logic circuit
13
that realizes a circuit function according to the selected circuit information.
FIG. 26
shows the detailed structure of the programmable logic circuit
13
based upon the multicontext technique. The programmable logic circuit
13
includes a circuit element
14
having input/output devices, logic circuit cells and wiring as in the above case and a configuration memory
15
connected to the circuit element
14
, however, the configuration memory
15
in the case of the programmable logic circuit
13
based upon the multicontext technique includes plural memory planes.
In the case of the programmable logic circuit
13
based upon the multicontext technique, in both structures of the FPGA type and the CPLD type (see FIG.
24
), each of plural circuit information pieces read from an external device in the programmable logic device
10
is written to each memory plane of the configuration memory
15
by the circuit information input controller
11
.
Of plural circuit information pieces written to the plural memory planes of the configuration memory
15
, the function and the connected state of the circuit element
14
are determined according to circuit information on the memory plane selected according to a selection signal from the circuit information selection controller
12
and circuits are reconfigured in the programmable logic device
10
.
For the format of circuit information used in a programmable logic device, there are a serial format and a parallel format and configuration operation differs depending upon these two circuit information formats. Configuration operation in the case of each circuit information format in the programmable logic device
1
shown in FIG.
22
and the programmable logic device
10
using the multicontext technique shown in
FIG. 25
will be described below.
[Structure of circuit information; (I) circuit information in serial format]
FIGS. 27
show the structure of circuit information in a serial format used in a conventional type programmable logic device. As shown in
FIG. 27A
, circuit information includes a header HDs, a data division DTs and a footer FTs. In a programmable logic device, circuit information in the serial format is treated as serial data, however, parallel transmission and parallel memory access are enabled by delimiting in a suitable unit such as 8 bits.
The header HDs has a preamble code showing the beginning of circuit information, length count showing th
Chang Daniel D.
Fuji Xerox Co. LTD
Morgan & Lewis & Bockius, LLP
Tokar Michael
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