Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-11-10
2001-10-02
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06298467
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to circuit design and, more particularly, to a system and method for reducing the undesirable effect of hysteresis (also called history effect) which degrades the performance of high performance circuits implemented using SOI CMOS processes.
2. Description of the Related Art
SOI (silicon-on-insulator) CMOS (complementary metal oxide semiconductor) devices/circuits have been demonstrated to operate faster than standard silicon bulk devices/circuits due to the improved current gain flowing through SOI devices. The faster operating speed is also due to the lack of parasitic junction capacitance, thus reducing the load being driven by the various gates/circuits implemented with SOI CMOS circuits. Typically, SOI circuits operate about 20 to about 35% faster than their bulk silicon counterparts.
There are however many effects related to SOI devices which may hinder the delay improvements claimed over bulk silicon devices. One such effect is the hysteresis effect, also called history effect. The hysteresis effect is caused by variations in the body potential (V
B
) due to body-source leakage and impact ionization at the body-drain interface. (See FIG.
3
). Impact ionization current increases the forward bias of the body voltage, which may lead to faster gate delays in dynamic equilibrium. In opposition to this, the relative magnitudes of forward and reverse bias currents reduce the forward bias over a sequence of transitions from equilibrium, resulting in slower gate delays. Both mechanisms (impact ionization and reduced forward bias currents) are competing against each other, resulting in slower or faster devices over time, depending on which mechanism dominates. A better understanding of hysteresis is illustrated in the FIGS. as described below.
The hysteresis effect results in a delay variation over time of the performance of circuits/gates. Referring to
FIG. 1
, an illustrative plot for delay versus time is shown for the delay variation for a similar circuit/gate implemented in both bulk and SOI.
FIG. 1
shows the quantitative worst-case-best case delay variations in time and the relative magnitude of these variations for both a bulk and an SOI circuit. The top curve shows that there is no delay variation for the bulk circuit. The bottom curve shows that in the best case, SOI will start being 20 to 35% faster than bulk, and that in time, the SOI circuit might become faster due to the hysteresis effect by up to 40%, and then in time, might slow down again to be the same delay as at the beginning.
The hysteresis effect has a very significant impact on the timing and performance of circuits/gates implemented in an SOI CMOS process since there may be uncertainty in the actual timing of the various circuits/gates throughout the system. This uncertainty may vary at any given time since it depends on the past history of the various signals controlling these circuits/gates. Timing cannot be predicted, simulated or estimated using standard circuit/gate timing techniques since it would be too computationally intensive to perform a simple analysis. Considering circuit design and timing methodologies for high performance circuit design, such a large delay variation cannot be ignored. Delay variations may be as high as 40%. To capture the timing uncertainty, most timing tools will have a built-in margin for error. Since the nature and magnitude of the delay variation due to hysteresis is somewhat pattern dependent and is also dependent on the initial state of the circuit, high level timing tools cannot ensure that the initial timing will be the best or worst case timing. The timing tools will need an added margin on either side of the timing. Even when considering the least damaging initial condition in terms of delay variation (which would be to consider that we are averaging the effects causing hysteresis), it would still be necessary to add half the maximum delay variations to capture worst case design conditions.
Referring to
FIG. 2
, another illustrative plot for delay versus time is shown for the delay variation for a similar circuit/gate implemented in both bulk and SOI. Using the same notation as in
FIG. 1
,
FIG. 2
shows the impact of timing margins added by timing tools if a default timing point was chosen as half way between the two extremes, which would lead to the smallest added timing margins on either side.
FIG. 2
shows the impact of adding margin on either side of the timing. If the worst case delay variation is 40%, half of that is 20% which would basically use all the possible claimed advantage of SOI over bulk as shown in FIG.
2
.
Adding enough timing margin at the system level to take into account the possible delay variation due to the hysteresis effect leads to a significant loss of performance for the overall system. For example, a system whose expected delay is T, or whose frequency is f=1/T, having a delay variation of 10%, leads to a loss of frequency of 10%. For high performance circuits, any loss due to an effect that cannot be controlled carefully is detrimental, especially considering that the delay variation due to the hysteresis effect may be as high as 40% (this means that a 1 GHz machine would only work at possibly 600 MHz).
Referring to
FIG. 3
, a cross-section of a partially-depleted SOI NMOS showing the various currents flowing through the devices is shown. I
CH
is a channel current, I
BJT
is a current created by the parasitic lateral bipolar device, I
R
is a recombination current, I
gi
is an impact ionization current and I
gt
is a thermal generation current. The definition of these currents is known in the art. A body potential V
B
at a silicon insulation layer (SiO
2
). A source (S) having a potential V
S
, a gate (G) having a potential V
G
and a drain (D) having a potential V
D
are shown. A potential difference between source and body is indicated as V
BS
=V
B
−V
S
.
FIG. 4
shows a rough representation of the I-V curves for such a SOI device shown in
FIG. 3
showing the different regions of operation of the SOI device.
Referring to
FIG. 5
, a standard CMOS inverter formed by SOI NMOS devices similar to those shown in
FIG. 3
as well as by SOI PMOS devices is provided. NMOS devices have a width Wn, and PMOS devices have for width Wp. In
FIG. 6
a more generic representation of a CMOS gate implemented with a pull up switch Sp controlled by pullup control signals, and a pulldown switch Sn controlled by pulldown control signals is shown. The switches Sp and Sn are made of a network of PMOS and NMOS devices respectively. Both the inverter and the generic gate are shown driving an output load CL, which in turn is representing another generic gate.
Relevant waveforms are shown in
FIGS. 7A-D
illustrating the hysteresis effect on the gate shown in
FIGS. 5 and 6
.
FIG. 7
shows the hysteresis phenomenon through four waveforms relevant to events in time occurring in the inverter/gate of
FIGS. 5 and 6
.
FIG. 7A
represents an input waveform Input(V).
FIG. 7B
represents an output waveform Output(V).
FIG. 7C
is a third waveform showing the variation of the body potential in the NMOS (in fact it is the body to source voltage V
BS
which is shown since it is more significant than the body potential, and is directly related to the threshold voltage of the device).
FIG. 7D
is a fourth waveform showing the body to source voltage V
BS
for the PMOS device.
FIG. 8
summarizes an average delay over time and further illustrates the variations of average delay defined as the half sum of the rise and fall delay (50% point) as described for FIG.
2
through the inverter/gate of
FIGS. 5 and 6
.
FIGS. 9 and 10
are summarize the curve of FIG.
8
and show the variations in body to source voltage for the NMOS (NFET) and PMOS (PFET) devices, respectively, for both the fall and rise transitions.
There are presently no alternate techniques aiming at reducing the impact of the hysteresis effect in SOI CMOS circuit other than increasing timing co
Chuang Ching-Te K.
Pelella Mario M.
Tretz Christophe R.
Do Thuan
F. Chau & Associates LLP
International Business Machines - Corporation
Smith Matthew
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