Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1999-04-14
2001-02-06
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S759000, C257S520000, C257S626000, C438S639000, C438S672000
Reexamination Certificate
active
06184584
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a miniaturized contact structure in a semiconductor substrate for connecting an upper interconnection with a diffused layer, and also relates to a method for forming the miniaturized contact.
2. Description of the Related Art
It has been still intensively proceeded to miniaturize each individual semiconductor element that is fabricated in the semiconductor substrate and to obtain a semiconductor device that includes these semiconductor elements integrated in the semiconductor substrate with a high-density. Such the miniaturization and the increase of density can not be achieved with a satisfactory result by only depending on a progress of the minimum feature size of (F) defined by the lithography technology.
If focusing attention on a surface of the semiconductor substrate, for example, the minimum line-width and the minimum space interval of a lower interconnection can be easily formed with (F). If focusing attention on a contact hole for use in connection of the lower interconnection with an upper interconnection formed in an insulator layer covering the semiconductor substrate, the minimum line-width and the minimum space interval of the upper interconnection can also be easily formed with (F).
However, a practicable semiconductor device can not be easily produced by combining such the lower interconnection, contact hole and upper interconnection. The reason why it is not easy may depend on the problems related to the lithography technology. Using freely a plurality of lithography processes and the like may produce the semiconductor device consisting of integrated semiconductor elements. At this stage, setting an alignment margin for aligning a photo mask is required between the lithography processes. Therefore, it is necessary to extend the line-width by the alignment margin at a layer of the lower interconnection at where the contact hole may reach. Thus, a line-pitch of the lower interconnection is necessary to set at (F)×2 or more.
In recent years, it has been possible by adopting the self-aligned contact hole to realize a line-width of (F) in a portion of the lower interconnection at where at least the contact hole reaches. It is also possible to form, within a space interval between the interconnections, an aperture having a contact size (a designed size) equivalent to a line-interval of (F).
A method proposed in IEICE TRANSACTION, Vol. E74, No. 4, pp. 818-826, 1991 will be exemplified below.
FIGS.
1
(
a
)-(
e
) are cross sectional views showing processes for realizing an aperture for a contact hole by reducing a real contact hole size in the case where a designed line-interval of (F) is equivalent to the designed contact hole size.
In the processes, the contact hole aperture may be realized first by reducing the real contact hole size if the designed line-interval of (F) were equivalent to the designed contact hole size.
This specification describes a case where no space is present between the interconnection and the contact hole for the convenience of understanding the difference between the present invention and the prior art in which the alignment margin is prepared between the interconnection and the contact hole.
As shown in FIG.
1
(
a
), a device isolation
201
and a diffused layer
202
are formed at a surface of a semiconductor substrate not depicted in the figure. A plurality of lower interconnections
203
is also formed on a lower interlayer film
204
a
deposited over the whole substrate. Then, an upper interlayer film
204
b
is deposited so as to bury the interconnections
203
as shown in FIG.
1
(
b
). A photo-resist
205
is further deposited on the upper interlayer film
204
b
and is defined to open a contact hole at a location between the interconnections
203
buried within the upper interlayer film
204
b
. A contact hole
206
having a size equal to an aperture diameter of the resist is then opened above the diffused layer
202
by dry etching.
After removing the resist, an HTO film (LPCVD High Temperature Oxide Film)
207
is formed over the upper surface of the upper interlayer film
204
b
as well as on a side-wall and the bottom of the contact hole
206
as shown in FIG.
1
(
c
). After performing a dry etchback for removing the HTO film
207
from the bottom of the contact hole
206
, a partial HTO film
207
′ may remain only on the inner wall of the contact hole
206
as shown in FIG.
1
(
d
).
Further, forming an upper interconnection
208
may finish the contact portion as shown in FIG.
1
(
e
) while this point is not described in the prior art.
As described above, the conventional technique is possible to arrange the lower interconnections and the contact hole with ensuring an insulating property by reducing the contact hole size finally even in a layout where the designed alignment margin is not present between the lower interconnections.
The conventional technique, however, may include the following disadvantages.
The opened bottom of the contact hole
206
shown in FIG.
1
(
d
) accepts the etchings twice according to the conventional technique, resulting extremely many defects within the diffused layer and in the substrate. With respect to the etching itself, the second etching is intended to remove the HTO film at a narrow and deep section by etchback. As the result, a probability of obtaining the desired aperture may be considerably lowered.
If reducing the size of the contact hole
206
, an area of a contact region between the contact hole and the diffused layer may be decreased and a resistivity of the contact region may increase inversely proportional to the contact area accordingly. In addition, reducing the size may generate a narrow and deep contact hole along the whole depth direction of the contact (a contact having a large aspect ratio). As the result, a contact resistance may be increased even in this stage (proportional to the contact depth and inversely proportional to the contact area). Further, finishing the contact by filling the contact hole with the interconnection layer may cause very serious problems such as a brake in the interconnection according to the coverage and burying property for the interconnection when obtaining a higher aspect ratio with such the structure.
An object of the present invention is to provide a miniaturized contact structure capable of forming an excellent contact without causing fatal problems in case of forming the contact, such as the increase of contact resistance and the disconnection. This may be achieved even when the contact must be formed under a condition where the alignment margin is not present in such the line-interval space.
Another object of the present invention is to provide a method for forming a miniaturized contact having such the structure.
SUMMARY OF THE INVENTION
The present invention provides a miniaturized contact in a semiconductor substrate. The contact comprises a diffused layer formed at a surface of the semiconductor substrate; an interlayer film for covering the diffused layer; a plurality of lower interconnections buried within the interlayer film; an upper interconnection disposed on the interlayer film; and a contact hole passing through the interlayer film for connecting the diffused layer with the upper interconnection. The contact hole has an aperture diameter equivalent to a space interval between the lower interconnections. The miniaturized contact further comprises a first buried conductor disposed within the contact hole only from the bottom to a height lower than that of the lower interconnections; a side-wall insulator disposed on a side-wall of the contact hole above the first buried conductor; and a second buried conductor disposed on the first buried conductor within the contact hole up to a height sufficient to contact with the upper interconnection.
The first buried conductor preferably includes a polysilicon, a metal silicide and a refractory metal. The second buried conductor preferably includes a polysilicon. Further, a single layer i
Clark Sheila V.
Hutchins, Wheeler & Dittmar
NEC Corporation
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