Method of forming copper dual damascene structure

Details Method of forming copper dual damascene structure Method of forming copper dual damascene structure

2001-02-15

2001-12-04

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S683000, C438S685000, C438S655000, C438S656000, C438S667000, C438S668000

Reexamination Certificate

active

06326306

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming a copper dual damascene structure, and more particularly to a method of forming a copper dual damascene structure, wherein a selectively deposited tungsten layer is formed on a silicide layer as a blocking layer of a copper contact.
2. Description of the Related Art
Conventional metal oxide semiconductor (MOS) contact technology commonly utilizes tungsten as a contact plug material. Tungsten has many advantages, such as the proper thermal expansion coefficient which is close to the one of silicon, the much less electromigration trend and the excellent step coverage ability. However, the high resistivity causes the increasing of the undesired RC time delay of the device used tungsten contacts and degrades the performance of the device.
FIG. 1
shows a cross-sectional view of a conventional MOS device and tungsten contacts. As shown in
FIG. 1
, the MOS device comprises source/drain regions
104
a
and
104
b
formed in a silicon substrate
100
and between shallow trench isolations
102
a
and
102
b
, a gate oxide layer
106
, a gate electrode
108
, spacers
110
a
and
102
b
, and silicide layers
112
a
and
112
b
. A dielectric layer
114
, tungsten contacts
116
a
and
116
b
, and metal lines
118
a
and
118
b
are also shown in FIG.
1
.
Owing to the high resistivity of tungsten, the tungsten contacts
116
a
and
116
b
are gradually unsatisfactory for the demand of the high speed of modern integrated circuits.
Dual damascene structures are more and more used amid the manufacture of the semiconductor device in view of fewer processing steps of their formation. In the dual damascene structures, the metal lines and the contacts are formed simultaneously. Lately, copper is used as the material of the lead lines and the contacts to replace tungsten for its much lower resistivity. However, once copper is used as the contact material, the barrier layer which is either a tantalum/tantalum nitride layer or a titanium/titanium nitride layer may not block copper effectively, and copper is very likely to diffuse into the active regions of the device during the processing phase and cause the failure of the device. Therefore, it is necessary to provide a novel contact technology to solve the problems of the conventional one mentioned above, and the method of the present invention is just the one.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to form a contact structure of fewer formation steps by forming lead lines and contacts simultaneously.
It is another object of this invention to provide form a low resistance and hence low RC time delay contact structure.
It is a further object of this invention to form a reliable low resistance copper contact structure by selectively depositing a tungsten layer as a blocking layer to prevent copper from diffusing into the active regions of the device.
To achieve these objects, and in accordance with the purpose of the invention, the invention uses a method comprising forming copper lead lines and copper contacts simultaneously and selectively depositing tungsten layers on silicide layers formed on the active regions. Firstly, a silicon substrate having a source region and a drain region therein and a gate electrode thereon is provided. Then silicide layers are formed on the source region and the drain region. Moreover, two dielectric layers are formed sequentially over the substrate. Furthermore, trenches are formed by etching the upper dielectric layer to expose the lower dielectric layer. Then contact holes are formed by further etching the bottom of the trenches into the lower dielectric layer to expose the silicide layers. Moreover, a selective tungsten chemical vapor deposition process is performed over the substrate to form tungsten layers on the silicide layers. Next a barrier layer is conformally formed over the substrate. Finally, a copper layer is conformally formed over the barrier layer to form a dual damascene structure.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 5130274 (1992-07-01), Harper et al.
patent: 5969422 (1999-10-01), Ting et al.
patent: 6013578 (2000-01-01), Jun
patent: 6197688 (2001-03-01), Simpson
patent: 6211084 (2001-04-01), Ngo et al.
patent: 6214731 (2001-04-01), Nogami et al.
patent: 6217721 (2001-04-01), Xu et al.

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