Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2001-03-06
2001-10-23
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C257S413000, C438S653000
Reexamination Certificate
active
06306743
ABSTRACT:
This application claims the benefit of Korean Application No. P2000-68405 filed Nov. 17, 2000, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for forming a gate electrode on a semiconductor substrate which reduces line resistance and formation of ohmic contacts.
2. Discussion of the Prior Art
Typically, to reduce gate resistance when forming a gate electrode on a semiconductor device, tungsten(W) having a specific resistance lower than WSi
x
by 1 order is deposited on polysilicon. The tungsten is then patterned to form a gate electrode. However, when tungsten reacts with polysilicon at a temperature of 600° C. or greater, a silicide forms at the boundary between tungsten and polysilicon. Therefore, tungsten nitride WN
x
is often used as a diffusion barrier layer between the tungsten and polysilicon, thereby forming a gate electrode having a W/WN
x
/polysilicon structure.
Although WN
x
is commonly used as the diffusion barrier layer, TiN may also be used. When W is deposited on TiN by a sputtering method, the grain size of W is smaller than the W/Si structure. In this scenario, resistance increases by a factor of two or more in comparison to pure W. Furthermore, the TiN is oxidized during the selective oxidation of the polysilicon layer. For these reasons, WN
x
is commonly used as the diffusion barrier layer. This is disclosed by Y. Akasaka in the article, “Low-Resistivity Poly-Metal Gate Electrode Durable for High-Temperature Processing” (IEEE Trans. Electron Devices, Vol. 43, pp. 1864-1869, 1996), and by B. H. Lee in the article “In-situ Barrier Formation for High Reliable W/barrier/poly-Si Gate Using Denudation of WN
x
on Polycrystalline”(IEDM, 1998).
One method for forming a gate electrode on a semiconductor device will be described with reference to the accompanying drawings.
FIGS. 1A
to
1
E are cross-sectional views showing the steps of a related art method for forming a gate electrode on a semiconductor device.
As shown in
FIG. 1A
, field oxide layers
12
are formed in a semiconductor substrate
11
in which an active region and a field region are defined. Using thermal oxidation a gate oxide layer
13
is formed on a surface of the semiconductor substrate
11
at a thickness of about 65 Å.
As shown in
FIG. 1B
, an undoped polysilicon layer
14
is formed by a low pressure chemical vapor deposition (LPCVD) method on the entire surface of the semiconductor substrate
11
at a thickness of about 2000 Å. N+ ions or P+ ions are then implanted into the polysilicon layer
14
. When the N+ ions or P+ ions are implanted, As or P ions are implanted into a negative-channel metal oxide semiconductor (NMOS) region while B or BF
2
ions are implanted into a positive-channel metal oxide semiconductor (PMOS) region using a photoresist as a mask.
Then an annealing process is performed in the polysilicon layer
14
for ten minutes and at a temperature of 800° C. to activate the impurity ions.
As shown in
FIG. 1C
, the semiconductor substrate
11
is washed by HF solution and then WN
x
layer
15
is formed on the polysilicon layer
14
at a thickness of 50~100 Å. A tungsten layer
16
is formed on the WN
x
, layer
15
at a thickness of about 1000 Å and a first insulating layer
17
is deposited on the tungsten layer
16
at a thickness of about 2000 Å.
The WN
x
layer
15
is used as a diffusion barrier between the tungsten layer
16
and the polysilicon layer
14
, and the first insulating layer
17
is used as a gate cap insulating layer later.
As shown in
FIG. 1D
, a photoresist(not shown) is deposited on the first insulating layer
17
and then patterned by exposure and developing processes to define a gate electrode region. The first insulating layer
17
, the tungsten layer
16
, the WN
x
layer
15
, the polysilicon layer
14
and the gate oxide layer
13
are selectively removed using the patterned photoresist as a mask to form a gate electrode
18
having a structure consisting of a tungsten layer
16
, a WN
x
layer
15
and a polysilicon layer
14
.
As shown in
FIG. 1E
, selective oxidation is performed in the gate electrode
18
to partially form an oxide layer (not shown) at the sides of the gate electrode
18
. Then a second insulating layer is formed on the entire surface of the semiconductor substrate
11
. The second insulating layer is etched back to form second insulating layer sidewalls
19
on both sides of the gate electrode
18
and the first insulating layer
17
.
However, the related art method for forming a gate electrode on a semiconductor device has several problems. When W/WN
x
is deposited on polysilicon, a W—Si—O—N layer forms at the boundary between tungsten and polysilicon during a later annealing process having a temperature of 800° C. or more. Thus, boundary resistance between tungsten and polysilicon increases thereby slowing the operation of the semiconductor device.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method for forming a gate electrode on a semiconductor substrate that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a method for forming a gate electrode on a semiconductor substrate that reduces the boundary resistance between tungsten and polysilicon, thereby preventing the operational speed of the semiconductor device from being slowed.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, in one aspect of the present invention there is provided a method for forming a gate electrode on a semiconductor substrate that includes forming a gate insulating layer on a semiconductor substrate, forming a polysilicon layer on the semiconductor substrate, forming a tungsten silicide layer on the polysilicon layer, forming a diffusion barrier layer on the tungsten silicide layer, forming a tungsten layer on the diffusion barrier layer, crystallizing the diffusion barrier layer, forming a first insulating layer on the tungsten layer, forming a gate electrode, forming an oxide layer, and forming a second insulating layer.
In another aspect, the present invention provides a method for forming a gate electrode on a semiconductor substrate that includes forming a gate insulating layer on a semiconductor substrate, forming a polysilicon layer on the semiconductor substrate, forming a tungsten silicide layer on the polysilicon layer, forming a diffusion barrier layer on the tungsten silicide layer, forming a tungsten layer on the diffusion barrier layer, crystallizing the diffusion barrier layer by performing an annealing process in the semiconductor substrate, and forming a first insulating layer on the tungsten layer. Then a gate electrode is formed by selectively patterning the first insulating layer, the tungsten layer, the diffusion barrier layer, the tungsten silicide layer, the polysilicon layer, and the gate insulating layer. Finally, a selective oxidation process is performed in the semiconductor substrate and a second insulating layer is formed.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5804499 (1998-09-01), Dehm et al.
patent: 5874353 (1999-02-01), Lin et al.
patent: 5923999 (1999-07-01), Balasubramanyam et al.
pa
Booth Richard
Hyundai Electronics Industries Co,. Ltd.
Morgan & Lewis & Bockius, LLP
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