Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2001-01-22
2001-12-25
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S225700
Reexamination Certificate
active
06333878
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, it relates to a semiconductor memory device including a spare memory cell repairing a faulty memory cell.
2. Description of the Prior Art
In general, there is a semiconductor memory device having a spare memory cell for repairing a faulty memory cell (hereinafter the term “spare” stands for “redundancy”). Such a conventional semiconductor memory device requires an internal circuit having a programming element for previously programming a faulty address (repair address) indicating a faulty memory cell position. This internal circuit detects that the programmed repair address is input in actual use, thereby using the spare memory cell in place of the faulty memory cell.
The conventional internal circuit uses a fuse blown with a laser beam as the programming element. The fuse serving as the programming element is laser-blown in accordance with the repair address, thereby programming the repair address.
However, a high-priced laser cutter is required for laser blowing with a heavy process burden for the laser blowing, while the blowing accuracy is dispersed. Further, the employment of the laser beam restricts the arrangement of components and wires. When employing the laser blowing, further, the program state may be fixed to restrict the repair efficiency.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a semiconductor memory device which can efficiently perform repair employing a spare with no laser blowing.
According to an aspect of the present invention, a semiconductor memory device comprises a memory cell array including a plurality of memory cells arranged in the form of a matrix and a plurality of spare memory cells for repairing faulty memory cells, and a plurality of address program circuits. Each of the plurality of address program circuits can program a repair address for repairing the faulty memory cell by a program voltage. The semiconductor memory device further comprises a pad externally receiving the program voltage and a voltage supply circuit selectively supplying the program voltage to each of the plurality of address program circuits.
Preferably, the voltage supply circuit of the semiconductor memory device includes a plurality of supply switches provided in correspondence to the respective ones of the plurality of address program circuits, each of the plurality of supply switches supplies the program voltage to the corresponding address program circuit in response to a control signal, and each of the plurality of address program circuits includes a program structure circuit including an electric fuse blown by the program voltage and a comparator circuit comparing match/mismatch of an input address and the repair address on the basis of the input address and the program state of the electric fuse for determining whether or not to perform repair.
Accordingly, a principal advantage of the present invention resides in that the semiconductor memory device comprises the plurality of address program circuits capable of performing programming with the program voltage and the voltage supply circuit selectively supplying the program voltage thereto, for enabling reliable programming while suppressing influence on a peripheral circuit.
Particularly when applying the program voltage every repair program, programming can be efficiently performed while suppressing influence on the peripheral circuit. Programming can be performed by blowing the electric fuse, whereby working steps are simplified and no laser cutter or the like is required.
Particularly when comprising a latch holding the program state, program information can be held with a simple circuit structure.
In particular, the address program circuit programs an address signal and a bank address signal. When having a plurality of banks, therefore, the banks can share the address program circuit.
In particular, a mode for checking the program state is provided in a program mode. Thus, programming can be reliably performed.
In particular, a chip enable signal is input as a trigger for reading the program state. Thus, high-speed spare determination and high-speed repair are enabled.
In particular, the program state is dividedly read a plurality of times. Thus, the electric fuse can be prevented from application of unnecessary stress.
In particular, a failure detection circuit is provided for detecting a failure of the electric fuse. Thus, initial failure of the electric fuse or the program state can be confirmed.
In particular, a fixing circuit is provided for arbitrarily setting the program state held in the latch. Thus, the spare memory cell can be tested independently of the program state.
Particularly when comprising a comparator circuit comparing a reference current with a current flowing through the electric fuse, the program state can be detected in high accuracy.
Particularly by employing a transfer circuit, the number of wires between the program structure circuit and the latch holding the program state can be reduced.
In particular, the semiconductor memory device collectively sends spare information. Thus, the number of wires connecting the address program circuit and a redundancy control circuit can be reduced.
In particular, the address program circuits include that capable of programming a row direction repair address and that capable of programming a column direction repair address, and read timings for the program state vary with the row direction and the column direction. Thus, a high-speed repair operation can be performed while reducing current consumption.
In particular, the address program circuit performs spare determination in parallel with an address setup operation. Thus, a high-speed repair operation is enabled.
According to another aspect of the present invention, a semiconductor memory device comprises a memory cell array including a plurality of memory cells arranged in the form of a matrix and a spare memory cell for repairing a faulty memory cell, and a plurality of address program circuits. Each of the plurality of address program circuits includes an electric fuse and can program a repair address for repairing the faulty memory cell by blowing the electric fuse with a program voltage, each of the plurality of memory cells includes a memory cell transistor having a pair of source/drain regions formed in a first impurity region and a gate electrode formed on a channel region between the pair of source/drain regions with an insulator film therebetween and a memory cell capacitor electrically connected with one of the pair of source/drain regions, and the electric fuse includes a pair of third impurity regions formed in the second impurity region, having the same conductivity type as the second impurity region and corresponding to the pair of source/drain regions of the memory cell transistor and a programming element, electrically connected to one of the pair of third impurity regions, corresponding to the memory cell capacitor.
Accordingly, another advantage of the present invention resides in that the semiconductor memory device comprises the electric fuse having a memory cell structure and programmed by the program voltage, whereby the electric fuse can be readily formed between wires or the like.
In particular, portions corresponding to the memory cell capacitors are connected to form a decoupling capacitor. Thus, a programming element having a large capacity can be formed in a small area.
According to still another aspect of the present invention, a semiconductor memory device comprises a memory cell array including a plurality of memory cells arranged in the form of a matrix and a plurality of spare memory cell columns each for repairing a faulty memory cell column including a faulty memory cell, a plurality of pairs of data lines for transferring data of the memory cell array, a plurality of pairs of spare data lines for transferring data of the plurality of spare memory cell columns, a data bus for transf
Le Vu A.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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