Interconnect structure of semiconductor device

Details Interconnect structure of semiconductor device Interconnect structure of semiconductor device

1999-11-16

2001-11-27

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S048000

Reexamination Certificate

active

06323556

ABSTRACT:

BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to an interconnect structure of a semiconductor device, more in detail, to the interconnect structure of the semiconductor device which can be easily observed when the interconnect structure is inspected by employing an electron beam inspection apparatus.
(b) Description of the Related Art
Since, with development of miniaturization and high integration of a semiconductor device, components of the semiconductor device including its interconnects are miniaturized and complicated, the inspection of the components becomes more and more difficult. Depending on the inspection techniques, the semiconductor device is operated during the inspection, wherein a non-destructive inspection of the components of the semiconductor device is conducted.
An electron beam inspection apparatus (hereinafter referred to as EB tester) is conventionally employed for non-destructive inspection of the components of the semiconductor device under the operation.
The EB tester utilizes the principle that an amount of secondary electrons generated at the position of measurement, the secondary electrons being generated upon irradiation of electron beams on the position of measurement of the semiconductor device under the operation, is proportional to the potential at the position of measurement. In the EB tester known as a non-contact inspection apparatus, the electron beams are irradiated on an interconnect of the semiconductor device to be inspected under vacuum, and a potential or a voltage of the interconnect is measured by means of the energy level of the secondary electrons generated from the irradiated part. The EB tester is frequently employed for inspecting the interior of the semiconductor device.
When, for example, a local damage or destruction is generated on a MOSFET, current is concentrated to the damaged or destructed part to produce a photon, the damaged or destructed part can be specified by detecting the photon by employing the EB tester.
The EB tester measures the amount of the secondary electrons having kinetic energy as low as several electron volts radiated from the position of measurement of the semiconductor device after conversion of the amount of the secondary electrons into a corresponding voltage. The EB tester usually has functions of observing secondary electron images and of measuring waveforms.
The function of observing the secondary electron images includes a function of observing a real time image while irradiating successive beams on the position of measurement of the semiconductor device and another function of observing a stroboscope image while irradiating a primary electron beam. In the function of measuring the waveforms, waveforms are obtained by irradiating a pulse beam having a variable phase to the position of measurement of the semiconductor device for radiation of secondary electrons and measuring the respective phases by employing a feedback loop with a spectrometer.
In the observation, a higher potential region of the secondary electrons obtained by the EB tester is shown as a dark side on a screen and a lower potential region is shown as a bright side, the higher potential region is shown as a high level. In the measurement, if unevenness exists on the surface of the semiconductor device during the observation with the EB tester, a secondary electron image reflecting the unevenness is obtained because the irradiated primary electron undergoes diffused reflection.
The interconnect structure of a semiconductor device is generally multi-layered with the miniaturization and the higher integration of the semiconductor device as shown in
FIGS. 1A and 1B
.
The interconnect structure
11
shown in
FIGS. 1A and 1B
includes a first layer subject interconnect
14
overlying an undercoat dielectric film
12
and to be subjected to the measurement. The interconnect structure
11
also includes other first layer interconnects
14
-
1
,
14
-
2
,
14
-
3
and
14
-
4
extending parallel to the subject interconnect
14
, a second layer interconnect
16
extending perpendicular to and overlying the first layer subject interconnect
14
, and a third layer interconnect
18
extending right above, the first layer subject interconnect
14
and having a width larger than that of the first layer subject interconnect
14
.
A first interlayer dielectric film
20
is formed between the first layer subject interconnect
14
and the second layer interconnect
16
. A second interlayer dielectric film
22
is formed between the second layer interconnect
16
and the third layer interconnect
18
, and a protection film
24
is formed on the third layer interconnect
18
.
The electron beam is generally directly irradiated to the position of measurement in the EB tester. In this respect, a problem arises that the potential of the first layer subject interconnect
14
or the position of deficiency cannot be specified when the first layer subject interconnect
14
in the above interconnect structure
11
is observed by employing the EB tester.
A first reason is as follows. Since the third layer interconnect
18
having a larger interconnect width overlies the first layer subject interconnect
14
in the multi-layered interconnect structure as shown in
FIG. 1B
, irradiation of the electron beam from the EB tester on the first layer subject interconnect
14
is blocked by the third layer interconnect
18
. Accordingly, the potential of the first layer subject interconnect
14
cannot e correctly measured.
Even when the width of the third layer interconnect
18
is not large, judgement whether the secondary electrons originate from the first layer subject interconnect
14
or the third layer interconnect
18
is difficult, and accordingly, the correct measurement of the first layer subject interconnect
14
cannot be conducted similarly to the case of the third layer interconnect
18
having the large width.
A second reason is as follows. In the measurement employing the EB tester, the interconnect path under the interlayer dielectric film is monitored by utilizing unevenness of the interlayer dielectric film. However, in the present semiconductor devices, the interlayer dielectric film on the interconnect of the multi-layered structure is generally polished for flattening. This makes it difficult to effectively observe the interconnect covered by the interlayer dielectric film by employing the EB tester.
A third reason is as follows. When another first layer subject interconnect
14
-
2
has a higher potential, and the first layer subject interconnect
14
and the other first layer sub-interconnects
14
-
1
,
14
-
3
and
14
-
4
have a lower potential, the potential of another first layer subject interconnect
14
-
2
is displayed as a bright side and the potentials of the first layer subject interconnect
14
and the other first layer interconnects
14
-
1
,
14
-
3
and
14
-
4
are displayed as a bright side. Since the flattened surface makes it difficult to observe the lower potential interconnects, it is difficult to specify the interconnect from which the bright side originates among the first layer subject interconnect
14
and the first layer interconnects
14
-
1
,
14
-
2
,
14
-
3
and
14
-
4
.
SUMMARY OF THE INVENTION
In view of the foregoing, an object of the present invention is to provide an interconnect structure of a semiconductor device having a configuration for easy observation by employing an EB tester and easy position identification.
The present invention provides a semiconductor device comprising a semiconductor substrate, a plurality of interconnect layers overlying said semiconductor substrate and including a top interconnect layer, a plurality of interlayer dielectric films each disposed between adjacent two of said interconnect layers, a top dielectric film disposed on said top interconnect layer, said top dielectric film having a plurality of convex or concave portions each disposed substantially right above a portion of a corresponding interconnect of at least one of said int

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