Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead
Reexamination Certificate
1999-07-29
2001-10-23
Clark, Jhihan B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
C257S756000, C257S776000, C257S798000
Reexamination Certificate
active
06307263
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to an integrated semiconductor chip.
If the area (layout structure) of an integrated semiconductor chip is considered, it is generally possible to identify so-called active regions and inactive regions on account of the structural differences in the topmost layer. By way of example, components or functional groups (for example transistors, memory cells) which effect a functionality of the semiconductor chip are disposed in the active regions; by contrast, no components or functional groups are contained in the inactive regions. With regard to the topographic construction of integrated semiconductor chips, modern fabrication processes require, in particular, homogeneous areal occupancy in all of the relevant process planes from the substrate up to and including a first metallization plane Therefore, the structural configuration of the process planes should largely be similar in the active and inactive regions of the chip. For this purpose, so-called modular dummy structures are provided within the inactive regions in the above mentioned process planes, the dummy structures being constructed similarly to the structures of the active regions. The use of modular dummy structures is already a common practice. They are primarily used for the following three reasons, reiterated briefly using key words:
a) for the production of identical layer hardnesses over the entire chip area by use of homogeneous areal occupancy underneath the respective topmost layer, important with regard to chemical mechanical polishing (CMP) and “Dishing”;
b) for homogenization of exposure illumination and defraction effects over the entire chip area, optical proximity effect (OPE); and
c) for homogenization and improvement of the etching process over the entire chip area, reactive ion etch (RIE) and “Micro Loading”.
For the operation of the semiconductor chip, it is desirable to homogenize the substrate potential of the chip as well as possible. The effect achieved by doing this is that the substrate potential is distributed uniformly for all components applied on the substrate. This results in a better, more uniform voltage supply for all the components distributed over the chip area. The wave propagation properties of voltage pulses on the electrical conductors are more predictable and more homogeneous against a uniform potential. Therefore, the wave guiding properties of superior wiring planes are also improved by a uniform substrate potential. Attempts have previously been made to achieve homogenization of the electrical substrate potential by using epitaxial substrates and by use of additional substrate contacts in the individual circuits. The known “latch-up” effect can be diminished, moreover, by using epitaxial substrates. One disadvantage of this procedure is that the application of the epitaxial layer to the substrate necessitates an additional, costly process step in the course of the fabrication process.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated semiconductor chip with modular dummy structures that overcomes the above-mentioned disadvantages of the prior art devices of this general type, in which an extensive homogenization of the substrate potential conditions on an integrated semiconductor chip are achieved and at the same time, the corresponding outlay in the course of the chip fabrication process is minimized.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated semiconductor chip, including a substrate and modular dummy structures disposed on the substrate and include a metallization plane with metal interconnects and a multiplicity of electrically conductive contact points disposed between the metal interconnects of the metallization plane and the substrate in areas of a chip area over which the dummy structures extend.
In accordance with an added feature of the invention, the modular dummy structures include a multiplicity of mutually identical sections, and one of the multiplicity of electrically conductive contact points is disposed between the metal interconnects of the metallization plane and the substrate in each of the multiplicity of mutually identical sections.
In accordance with an additional feature of the invention, each of the multiplicity of mutually identical sections, includes: a portion of the substrate corresponding to a size of a respective section of the multiplicity of mutually identical sections; zones formed of polysilicon disposed above the substrate; a doping zone disposed in the substrate and spaced apart from the zones formed of polysilicon; and one of the multiplicity of electrically conductive contact points electrically conductively connected to the doping zone and to the metal interconnects of the metallization plane.
In accordance with another feature of the invention, the substrate has trenches formed therein disposed underneath the zones formed of polysilicon and including an oxide filling the trenches resulting in oxide-filled trenches.
In accordance with a further added feature of the invention, the doping zone and the substrate are composed of doped silicon having a same doping polarity, the doped silicon in the doping zone being doped with a high concentration and the doped silicon in the substrate being doped with a low concentration.
In accordance with a further additional feature of the invention, the zones formed of polysilicon and the oxide-filled trenches of neighboring sections of the multiplicity of mutually identical sections of the dummy structures are embodied as respective shared zones.
In accordance with a concomitant feature of the invention, the dummy structures have a layout structure in regions of the chip area over which the dummy structures extend, the layout structure, includes:
an oxide, the substrate having trenches formed therein and the oxide disposed in and filling the trenches resulting in oxide-filled trenches;
zones formed of polysilicon disposed on the substrate over an area of the oxide-filled trenches, the zones formed of polysilicon covering only part of the area of the oxide-filled trenches, the oxide-filled trenches and the zones formed of polysilicon disposed contiguously over an entire region of the chip area over which the dummy structures extend and enclose regions not having the oxide-filled trenches and the zones formed of polysilicon, the regions disposed at regular intervals and are oriented parallel in regards to each other;
doping zones disposed in the substrate in the regions surrounded by the zones formed of polysilicon and the oxide-filled trenches;
the electrically conductive contact points applied to the doping zones and, via the doping zones, establish electrically conductive connections with the substrate, the electrically conductive contact points covering only a part of each of the doping zones;
the metal interconnects of the metallization plane are strip shaped metal interconnects oriented in a cruciform fashion at regular intervals and, in each direction, parallel to one another, and are disposed such that the metal interconnects of the metallization plane are situated in each case at right angles to one another forming crossover areas which are situated in each case above one of the electrically conductive contact points and cover the electrically conductive contact points; and
the metal interconnects of the metallization plane are electrically conductively connected to the electrically conductive contact points in a region of the crossover areas.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated semiconductor chip with modular dummy structures, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range
Savignac Dominique
Schneider Helmut
Clark Jhihan B
Greenberg Laurence A.
Lerner Herbert L.
Siemens Aktiengesellschaft
Stemer Werner H.
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