Electronic digital logic circuitry – Interface – Supply voltage level shifting
Reexamination Certificate
2000-01-27
2001-10-23
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Supply voltage level shifting
C326S056000, C326S057000, C326S058000, C326S068000, C326S080000
Reexamination Certificate
active
06307397
ABSTRACT:
RELATED APPLICATIONS
This application is related to the following applications, which are filed on the same date herewith and incorporated herein by reference:
Application entitled “MIXED SWING VOLTAGE REPEATERS FOR HIGH RESISTANCE OR HIGH CAPACITANCE SIGNAL LINES AND METHODS THEREFOR” filed by inventors Gerhard Mueller and David R. Hanson on the same date.
Application entitled “FULL SWING VOLTAGE INPUT/FULL SWING VOLTAGE OUTPUT BI-DIRECTIONAL REPEATERS FOR HIGH RESISTANCE OR HIGH CAPACITANCE B-DIRECTIONAL SIGNAL LINES AND METHODS THEREFOR” filed by inventors Gerhard Mueller and David R. Hanson on the same date.
BACKGROUND OF THE INVENTION
The present invention relates to repeater circuits for high resistance and/or high capacitance signal lines on an integrated circuit. More particularly, the present invention relates to reduced voltage input/reduced voltage output repeaters which, when employed on a high resistance and/or high capacitance signal line, reduces the signal propagation delay, power dissipation, chip area, electrical noise, and/or electromigration.
In some integrated circuits, there exist signal lines which span long distances and/or coupled to many circuits. In modern dynamic random access memory circuits, for examples, certain unidirectional signal lines such as address lines may be coupled to many circuits and may therefore have a high capacitive load and/or resistance associated therewith. Likewise, certain bi-directional lines such as read write data (RWD) lines may also be coupled to many circuits and may therefore also have a high capacitive load and/or resistance associated therewith. The same issue also applies for many signal lines in modern microprocessors, digital signal processors, or the like. By way of example, the same issue may be seen with loaded read data lines and write data lines of memory circuits, clock lines of an integrated circuit, command lines, and/or any loaded signal carrying conductor of an integrated circuit. The propagation delay times for these signal lines, if left unremedied, may be unduly high for optimal circuit performance.
To facilitate discussion,
FIG. 1
illustrates an exemplary signal line
100
, representing a signal conductor that may be found in a typical integrated circuit. Signal line
100
includes resistors
102
and
104
, representing the distributed resistance associated with signal line
100
. Resistors
102
and
104
have values which vary with, among others, the length of signal line
100
. There are also shown capacitors
106
and
108
, representing the distributed capacitance loads associated with the wire or signal bus and the circuits coupled to signal line
100
.
The resistance and capacitance associated with signal line
100
contribute significantly to a signal propagation delay between an input
110
and an output
112
. As discussed in a reference entitled “Principles of CMOS VLSI design: A Systems Perspective” by Neil Weste and Kamran Eshraghian, 2nd ed. (1992), the propagation delay of a typical signal line may be approximately represented by the equation
t
delay
=0.7(
RC
)(
n
)(
n+
1)/2 Eq. 1
wherein n equals the number of section, R equals the resistance value, C equals the capacitance value. For the signal line of
FIG. 1
, the propagation delay is therefore approximately 2.1 RC (for n=2).
If the resistance value (R) and/or the capacitance value (C) is high, the propagation delay with signal line
100
may be significantly large and may unduly affect the performance of the integrated circuit on which signal line
100
is implemented. For this reason, repeaters are often employed in such signal lines to reduce the propagation delay.
FIG. 2
depicts a signal line
200
, representing a signal line having thereon a repeater to reduce its propagation delay. Signal line
200
is essentially signal line
100
of
FIG. 1
with the addition of a repeater
202
disposed between an input
210
and an output
212
. In the example of
FIG. 2
, repeater
202
is implemented by a pair of cascaded CMOS inverter gates
204
and
206
as shown. For ease of discussion, repeater
202
is disposed such that it essentially halves the distributed resistance and capacitance of signal line
200
.
In this case, the application of Eq. 1 yields a propagation delay of 0.7 (RC)+t
DPS
+t
DPS
+0.7 (RC) or 1.4 (RC)+2t
DPS
, wherein t
DPS
represents the time delay per inverter stage. Since t
DPS
may be made very small (e.g., typically 250 ps or less in most cases), the use of repeater
202
substantially reduces the propagation delay of the signal line, particularly when the delay associated with the value of R and/or C is relatively large compared to the value of t
DPS.
Although the use of CMOS repeater
202
proves to be useful in reducing the propagation delay for some signal lines, such an CMOS inverter-based repeater approach fails to provide adequate performance in reduced voltage input/reduced voltage output applications. Reduced voltage input refers to input voltages that are lower than the full V
int
or V
DD
, the internal voltage at which the chip operates. By way of example, if V
int
is equal to 2 V, reduced voltage signal may swing from 0-1 V or −0.5 V to 0.5 V. In some cases, the reduced voltage may be low enough (e.g., 1 V) that it approaches the threshold voltage of the transistors (typically at 0.7 V or so). Likewise, reduced voltage output refers to output voltages that are lower than the full V
int
, the internal voltage at which the chip operates.
To appreciate the problems encountered when reduced voltage signals are employed in the inverter-based repeater, which is operated at V
int
or V
DD
, consider the situation wherein the input of the inverter is logically high but is represented by a reduced voltage signal (e.g., around 1 V). In this case, not only does the n-FET of the CMOS inverter stage conduct as expected but the p-FET, which is in series thereto, may also be softly on, causing leakage current to traverse the p-FET. The presence of the leakage current significantly degrades the signal on the output of the repeater circuit (and/or greatly increasing power consumption).
Despite the fact that CMOS inverter-based repeaters do not provide a satisfactory solution in reduced voltage applications, chip designers continue to search for ways to implement repeaters in the reduced voltage integrated circuits. Reduced voltage signals are attractive to designers since reduced voltage signals tend to dramatically reduce the power consumption of the integrated circuit. Further, the use of reduced voltage signals leads to decreased electromigration in the conductors (e.g., aluminum conductors) of the integrated circuit. With reduced electromigration, the chance of developing voids or shorts in the conductors is concomitantly reduced. Further, the reduction in the power consumption also leads to decreased electrical noise since less charge is dumped on the ground and power buses of the integrated circuit at any given time.
As can be appreciated from the foregoing, there is a desire for improved techniques for implementing reduced voltage input/reduced voltage output repeaters on the high resistance and/or high capacitance signal lines of an integrated circuit.
SUMMARY OF THE INVENTION
The invention relates, in one embodiment, to a method in an integrated circuit for implementing a reduced voltage repeater circuit on a signal line having thereon reduced voltage signals. The reduced voltage signals has a voltage level that is below V
DD
. The reduced voltage repeater circuit is configured to be coupled to the signal line and having an input node coupled to a first portion of the signal line for receiving a first reduced voltage signal and an output node coupled to a second portion of the signal line for outputting a second reduced voltage signal. The method includes coupling the input node to the first portion of the signal line. The input node is coupled to an input stage of the reduced voltage repeater circuit. The input stage is configured to recei
Hanson David R.
Mueller Gerhard
Braden Stanton C.
Infineon-Technologies AG
Tan Vibol
Tokar Michael
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