Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-06-09
2001-12-11
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S372000, C257S373000, C257S903000
Reexamination Certificate
active
06329693
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to an SRAM (Static Random Access Memory) and a method for manufacturing the same.
2. Description of the Related Art
FIG. 27
shows an equivalent circuit diagram of an SRAM memory cell. A load transistor Q
5
and a driver transistor Q
3
form an inverter. A load transistor Q
6
and a driver transistor Q
4
form an inverter. The inverters are electrically connected to each other to form a flip-flop.
A transfer transistor Q
2
connects an output cell node
1000
of the inverter that is formed by the load transistor Q
6
and the driver transistor Q
4
and a bit line (BL). A gate electrode of the transfer transistor Q
2
is electrically connected to a word line.
Source regions of the load transistors Q
5
and Q
6
electrically connect to a power supply line V
DD
. Source regions of the driver transistors Q
3
and Q
4
electrically connect to a ground line V
SS
.
A transfer transistor Q
1
connects an output cell node
1002
of the inverter that is formed by the load transistor Q
5
and the driver transistor Q
3
and a bit line (/BL). A gate electrode of the transfer transistor Q
1
is electrically connected to a word line.
The flip-flop retains a state in which the cell node
1000
is at a voltage of 3V, for example, and the cell node
1002
is at a voltage of 0V, for example, as “1”, for example. Also, the flip-flop retains a state in which the cell node
1000
is at a voltage of 0V, for example, and the cell node
1002
is at a voltage of 3V, for example, as “0”, for example.
An SRAM may suffer a problem of an &agr;-ray soft error. Materials for wiring layers, molding resin, and the like contain a very small amount of radioactive substances. The radioactive substances generate &agr;-rays. The &agr;-ray soft error is a phenomenon in which retained data is destroyed due to the &agr;-ray. The destruction of retained data by the &agr;-ray soft error will be described below in detail, with reference to the accompanying figure.
FIG. 25
is a cross-sectional view of a silicon substrate
200
in which the load transistor Q
6
and the driver transistor Q
4
are formed. The silicon substrate
200
is of a p-type. An n-well
202
and a p-well
204
are formed adjacent to each other. A source
212
and a drain
214
of the driver transistor Q
4
are formed in the p-well
204
. A p-type well contact region
216
is formed in the p-well
204
. The well contact region
216
is isolated from the source
212
by a field oxide film
206
. The well contact region
216
and the source
212
are electrically connected to the ground line V
SS
.
A source
218
and a drain
220
of the load transistor Q
6
are formed in the n-well
202
. An n-type well contact region
222
is formed in the n-well
202
. The well contact region
222
is isolated from the source
218
by a field oxide film
210
. The well contact region
222
and the source
218
are electrically connected to the power supply line V
DD
. The drain
220
is isolated from the drain
214
by a filed oxide film
208
.
Next, the destruction of retained data by the &agr;-ray soft error will be described with reference to
FIGS. 25 and 26
. As shown in
FIG. 25
, when the cell node
1000
is at 3V, for example, the drain
214
is at 3V, and the p-well
204
is biased to the ground line V
SS
. Therefore, because a diode formed by the drain
214
and the p-well
204
is inversely biased, a depletion layer is formed.
In this state, if an &agr;-ray passes through the drain
214
and the p-well
204
and reaches the silicon substrate
200
, the depletion layer of the diode is warped by the &agr;-ray. As a result, electron-hole pairs are cut along the pass of the &agr;-ray. As shown in
FIG. 26
, the holes flow into the well contact region
216
and into the ground line V
SS
. The electrons flow into the drain
214
that is at a high voltage. The flows of the holes and the electrons lower the drain voltage. As a result, the retained data is destroyed. In other words, in this example, the state of the cell node
1000
changes from 3V to 0V, and therefore the state “1” changes to “0”.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor memory device with a structure that is difficult to cause harmful effects on the memory function and a method for manufacturing the same.
In accordance with one embodiment of the present invention, a semiconductor memory device has a semiconductor substrate defining a main surface, and a peripheral circuit region and an SRAM memory cell region in the main surface. The semiconductor memory device comprises a first well, a second well of a first conductivity type, a third well of a second conductivity type, a device element isolation structure, an embedded layer of the second conductivity type, a driver transistor, a load transistor, and an impurity region of the second conductivity type. The first well is formed in the peripheral circuit region, and the second well is formed in the memory cell region. The second well is shallower than the first well. The driver transistor is formed in the second well. The impurity region is formed in the second well. The impurity region is a drain of the driver transistor. The impurity region is an element that composes a cell node. The third well is formed in the memory cell region. The third well is shallower than the first well. The load transistor is formed in the third well. The device element isolation structure is formed in the memory cell region. The device element isolation structure isolates the driver transistor from the load transistor. The second well and the third well are formed to extend to a location under the device element isolation structure. The embedded layer is formed under the second well and under an area where at least the impurity region is located. The embedded layer forms a junction with the second well. The embedded layer is fixed at a potential that prevents carriers of the second conductivity type in the embedded layer from flowing into the second well.
The semiconductor memory device in accordance with the embodiment achieves the following advantages.
The miniaturization of a memory cell must address two conflicting issues. The length of the device element isolation structure (such as a semi-recessed LOCOS oxidation layer) of the memory cell area needs to be shortened in order to miniaturize the memory cell. On the other hand, to prevent the generation of a parasitic MOS leak current that causes latch-up, the spacing between one well and source/drain of another well formed adjacent to the one well needs to be longer than a certain distance. Accordingly, when the length of the device element isolation structure is shortened to miniaturize the memory cell, the spacing between one well and the source/drain of another well formed adjacent to the one well may become too short to an extent that a parasitic MOS leak current may be readily generated. However, in accordance with the embodiment of the present invention, the length of the device element isolation structure can be reduced for the miniaturization of the memory cell, while the distance between one well and the source/drain of another well formed next to the one well can be prevented from becoming too short.
In a semiconductor memory device in accordance with one embodiment of the present invention, the wells in the peripheral circuit region and the wells in the memory cell region may be different in depth. In other words, the second and third wells formed in the memory cell region are shallower than the first well formed in the peripheral circuit region. Accordingly, this structure can reduce an overlapped area between the second well and the third well beneath the device element isolation structure. The reason for this will be described below in conjunction with the discussion of the embodiments. Accordingly, in a semiconductor memory device in accordance with the present invention, the length of the device element isolatio
Hogan & Hartson L.L.P.
Ngo Ngan V.
Seiko Epson Corporation
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