Method of forming flat wiring layer

Details Method of forming flat wiring layer Method of forming flat wiring layer

1999-09-02

2001-02-20

Bowers, Charles (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S633000, C438S637000, C438S638000, C438S639000, C438S596000

Reexamination Certificate

active

06191027

ABSTRACT:

This application is based on Japanese Patent Application No. 9-137931 filed on May 12, 1997, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
a) Field of the Invention
The present invention relates to a method of forming a flat wiring layer with a damascene method, and more particularly to a flat wiring layer forming method capable of forming a low resistance and high reliability flat wiring layer by depositing a conductive layer inlaid in connection holes and interconnect grooves formed in an insulating film and thereafter planarizing the conductive layer.
b) Description of the Related Art
A flat wiring layer forming method with a damascene method is already known, for example, as illustrated in
FIGS. 28
to
30
(e.g., refer to “DUAL DAMASCENE: A ULSI WIRING TECHNOLOGY”, Carter W. Kaanta et al. Jun. 11-12, 1991 VMIC Conference).
At the process shown in
FIG. 28
, after wirings
2
A and
2
B are embedded in a surface layer of an insulating film
1
, the surface of the insulating film
1
is planarized by CMP (chemical mechanical polishing). Another insulating film
3
is formed on the planarized surface of the insulating film
1
.
A resist pattern
4
having holes
4
a
and
4
b
corresponding to connection portions to the wirings
2
A and
2
B is formed on the insulating film
3
. Another resist pattern
5
is formed on the resist pattern
4
, the resist pattern
5
having an interconnect hole coupling the holes
4
a
and
4
b
of the resist pattern
4
.
In the process shown in
FIG. 29
, by using the resist patterns
4
and
5
as a mask, the insulating film
3
is dry-etched to form connection holes
3
a
and
3
b
reaching the wirings
2
A and
2
B and an interconnect groove
3
A coupling the connection holes
3
a
and
3
b,
respectively in the insulating film
3
. The connection holes
3
a
and
3
b
correspond to the holes
4
a
and
4
b
of the resist pattern
4
, and the interconnect groove
3
A corresponds to the hole
5
A of the resist pattern
5
.
In the process shown in
FIG. 30
, a W (tungsten) layer
6
is deposited on the insulating film
3
by CVD (chemical vapor deposition), the W layer
6
filling the connection holes
3
a
and
3
b
and interconnect groove
3
A. The W layer
6
is planarized by CMP to leave a portion of the W layer
6
in the connection holes
3
a
and
3
b
and interconnect groove
3
A.
With this conventional technique, the material of the wiring
6
A is tungsten having a high resistivity so that a wiring resistance becomes high.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a novel flat wiring layer forming method capable of forming a flat wiring layer having low resistance and high reliability.
According to one aspect of the present invention, there is provided a method of fabricating a semiconductor device, comprising the steps of: a) providing a substrate having an insulating layer thereon; b) forming a connection hole including a first sub-hole and a second sub-hole mutually aligned and connected in the insulating layer, wherein the first sub-hole has a first diameter and the second sub-hole has a second diameter larger than the first diameter; c) forming a first conductive layer over the substrate; d) removing the first conductive layer to a thickness so as to form a side wall spacer film on a side wall of the second sub-hole and a plug film in the first sub-hole; e) forming a barrier metal layer over the substrate to cover the side wall spacer and the plug film; f) forming a second conductive layer over the substrate to fill space in the connection hole; and g) chemical mechanical polishing the second conductive layer.
If the second conductive layer is made of wiring material having a low resistivity, the resistance of a wiring layer can be lowered.
When the first conductive layer is etched, the side wall spacer film is left on the side wall of the second sub-hole and the plug in the first sub-hole. It is therefore possible to improve the step coverage of the barrier metal layer.
According to a second aspect of the present invention, there is provided a method of fabricating a semiconductor device, comprising the steps of: a) providing a substrate having an insulating layer thereon; b) forming a connection hole including a first sub-hole and a second sub-hole mutually aligned and connected in the insulating layer, wherein the first sub-hole has a first diameter and the second sub-hole has a second diameter larger than the first diameter; c) forming a first conductive layer over the substrate; d) removing the first conductive layer to a thickness so as to form a side wall spacer film on a side wall of the second sub-hole and a plug film in the first sub-hole from the first conductive layer, respectively, wherein the plug film has a seam therein; e) forming a barrier metal layer over the substrate to cover the side wall spacer and the plug film; f) forming a second conductive layer over the substrate to fill space in the connection hole; and g) planarizing the second conductive layer to provide a damascene structure in the connection hole.
If the second conductive layer is made of wiring material having a low resistivity, the resistance of a wiring layer can be lowered.
When the first conductive layer is etched, the side wall spacer film is left on the side wall of the second sub-hole and the plug in the first sub-hole. It is therefore possible to improve the step coverage of the barrier metal layer. A void or seam in the plug made of the first conductive layer can be reliably covered with the barrier layer so that the reliability of the wiring layer can be improved.


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K. Ueno, et al., “A Quarter-Micron Planarized Interconnection Technology with Self-Aligned Plug”, IEDM 1992, pp. 305-308.
T. Zettler, et al., “Self-Reconstructing Metallization—A Novel Planar Process for VLSI Metallization”, VMIC Conference, Jun. 8-9, 1993, pp. 359-365.
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K. Suguro et al., “Cu Inlaid Interconnections Formed by Dual Damascene”, ULSI Research Laboratories, Manufacturing Engineering Research Center, Semiconductor Division, Toshiba Corporation, pp. 42-47.
K. Kikuta, et al., “Aluminum-Germanium-Copper Multilevel Damascene Process Using Low Temperature Reflow Sputtering and Chemical Mechanical Polishing”, IEDM 1994, pp. 101-104.

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