Method of producing semiconductor device

Details Method of producing semiconductor device Method of producing semiconductor device

1992-12-28

2001-12-11

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Introduction of conductivity modifying dopant into...

Diffusing a dopant

C438S629000, C438S637000, C438S642000, C438S658000

Reexamination Certificate

active

06329274

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a method of producing a semiconductor device having a contact hole between different electroconductive layers, and more specifically relates to a method of filling the contact hole with an interposed layer to achieve reduction of contact resistance.
Brief description is firstly given for the conventional method of producing a semiconductor device with reference to FIGS.
2
(
a
)-
2
(
c
). In the step of FIG.
2
(
a
), an N type impurity diffusion layer
12
is formed in a silicon substrate
11
. In the step of FIG.
2
(
b
), a contact hole
14
is formed in an insulating film
13
disposed over the substrate
11
. Thereafter, the step of FIG.
2
(
c
) is carried out to form a lead pattern layer
15
composed of aluminum, silicide or high-melting-temperature metal.
In the conventional semiconductor device of sub-micron scale, depth of the impurity diffusion layer
12
shown in FIG.
2
(
a
) is controlled less than 0.4 &mgr;m, thereby causing a defect called an alloy spike under the lead pattern
15
made of aluminum in the contact hole
14
, which tends to reduce the junction breakdown voltage of the impurity diffusion layer
12
. Further, in case that the lead pattern layer
15
is made of silicide or high-melting-temperature metal, the impurity concentration is decreased at the junction of impurity diffusion layer
12
of silicon in the contact hole
14
, thereby increasing contact resistance between the lead pattern layer
15
and the impurity diffusion layer
12
.
FIG. 10
is a sectional view showing one example of the conventional contact structure between a low resistivity region and a metal lead electrode in an insulating gate field effect transistor. A P
+
type drain or source region
101
is formed in a semiconductor substrate
106
by ion implantation. A contact hole is formed in a field insulating film
103
. Thereafter, a metal electrode
104
composed, for example, of aluminum is formed to define a drain electrode or source electrode.
In the above described prior art construction, impurity diffusion is carried out by ion implantation to form P
+
type region. As shown in
FIG. 11
, in the impurity diffusion by the ion implantation, the activated carrier density is decreased on the surface of the substrate, thereby causing increase in the contact resistance with respect to the metal electrode. In addition, damage may be disadvantageously caused on the substrate surface layer due to the ion implantation. Further, aspect ratio of a step portion in a contact hole may be increased when an opening area of the contact hole is reduced for more efficient integration of transistor circuits, thereby causing opening of the metal lead pattern layer and causing defects due to electromigration at a contact hole edge and due to stress-migration.
SUMMARY OF THE INVENTION
In view of the above noted drawbacks of the prior art, an object of the invention is to produce a semiconductor device in which a surface impurity concentration is increased on the impurity diffusion layer or first electroconductive layer formed in the substrate so as to decrease the contact resistance relative to the lead pattern layer or second electroconductive layer.
In order to realize the above noted object, the inventive method of producing a semiconductor device is comprised of the first step of forming an insulating film on a first electroconductive layer and then forming a contact hole to expose a part of the first electroconductive layer, the second step of forming an activated surface of the exposed part in the contact hole, the third step of applying to the activated surface a gas containing an impurity component to form an impurity adsorption film, and the fourth step of filling the contact hole with a second electroconductive layer.
In a preferred form, annealing may be carried out after the third or fourth step to form an impurity-doped sub-layer in the first electroconductive layer.
Further, in case that the second electroconductive layer is composed of silicide of high-melting-temperature metal such as tungsten silicide, another impurity adsorption layer is formed on the second electroconductive layer and then is annealed to dope the impurity into the silicide of high-melting-temperature metal to thereby reduce resistivity of the second electroconductive layer.
A layer containing impurity doped from the impurity adsorption film has a quite high surface impurity concentration more than 10
70
/cm
3
and can be provided in a great doping depth, thereby eliminating the defect of increase in the contact resistance due to the alloy spike or due to reduction of the surface concentration.


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Wolf, S., et al, Silicon Processing for the VLSI Era, vol. 1, pp. 264-265, 1986.*
Wolf, S., et al, Silicon Processing for the VLSI Era, vol. 2, pp. 102-103, 117-120, 1990.*
Gong, S., F., et al, “A Metal Oxide...Solid Phase Doping”, J. Appl. Phys., 65 (11) , Jun. 1, 1989 pp. 4435-4437.

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