Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1998-03-31
2001-12-04
Wiley, David (Department: 2155)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S038110, C714S041000, C710S260000, C710S261000, C703S023000, C703S026000
Reexamination Certificate
active
06327676
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to test equipment, and more particularly to test equipment adapted to inject an electronic disturbance into an electronic system while such system is in operation.
As is known in the art, test equipment have been used in a wide variety of applications. One application is to test integrated circuits. For example, in such application, test equipment is used to introduce a logic level, i.e., a relatively static input voltage into the integrated circuit to test whether the integrated circuit produces a proper output.
The need also exists to test higher level systems, such as, for example, large capacity data storage systems. These large capacity storage systems are used with large host(e.g., main frame or open system) computer systems. The computer system generally includes data processors which perform many operations on data introduced to the computer system through peripherals included in the data storage system. The results of these operations are output to peripherals, included in the storage system.
One type of data storage system is a magnetic disk storage system. Here a bank of disk drives and the host computer system are coupled together through an interface. The interface includes CPU, or “front end”, controllers and “back end” disk controllers. The interface operates the controllers in such a way that they are transparent to the computer. That is, data is stored in, and retrieved from, the bank of disk drives in such a way that the host computer system merely thinks it is operating with one host computer system memory. One such system is described in U.S. Pat. No. 5,206,939, entitled “System and Method for Disk Mapping and Data Retrieval”, inventors Moshe Yanai, Natan Vishlitzky, Bruno Alterescu and Daniel Castel, issued Apr. 27, 1993, and assigned to the same assignee as the present invention.
As described in such U.S. Patent, the interface may also include, in addition to the CPU controllers and disk controllers, addressable cache memories. The cache memory is a semiconductor memory and is provided to rapidly store data from the host computer system before storage in the disk drives, and, on the other hand, store data from the disk drives prior to being sent to the host computer. The cache memory being a semiconductor memory, as distinguished from a magnetic memory as in the case of the disk drives, is much faster than the disk drives in reading and writing data.
The CPU controllers, disk controllers and cache memory are interconnected through a backplane printed circuit board. More particularly, disk controllers are mounted on disk controller printed circuit boards. CPU controllers are mounted on CPU controller printed circuit boards. And, cache memories are mounted on cache memory printed circuit boards. The disk controller, CPU controller and cache memory printed circuit boards plug into the backplane printed circuit board. In order to provide data integrity in case of a failure in a controller, the backplane printed circuit board has a pair of buses. One set the disk controllers is connected to one bus and another set of the disk controllers is connected to the other bus. Likewise, one set the CPU controllers is connected to one bus and another set of the CPU controllers is connected to the other bus. The cache memories are connected to both buses. Thus, the use of two buses provides a degree of redundancy to protect against a total system failure in the event that the controllers, or disk drives connected to one bus fail.
In one system, the communication to the controllers and the cache memories is through a pair of bi-directional lines. Typically one bi-directional line is for data and the other bi-directional line is for control signals. As noted above, each controllers is connected to only one of the buses and, therefore, only one pair of bi-directional lines are electrically connected to the controllers; however, because each one of the cache memories is connected to both buses, each cache memory has two pairs of bi-directional lines.
One such data storage system is an asynchronous system. In such asynchronous system, when a controller wishes to read data from an addressed memory, the addressed memory places the data and a clock pulse on the bus. The data and the clock travel along the bus to the controller, the controller receives the data and clocks the data into the controller using the clock placed on the bus by the addressed memory. When the controller wishes to have data written into an addressed memory, the controller places the data on the bus and the addressed memory must strobe the data on the bus into itself. However, because the system is asynchronous, the addressed memory may not be ready to accept the data on the bus. Therefore, when addressed by the controller, the memory places a clock on the bus, the clock runs to the controller, the controller detects the clock sent by the addressed memory and places the data on the bus. The data runs back to the addressed memory, and then, after a predetermined round-trip time, the addressed memory clocks in the data. A typical round-trip time may be in the order of about 100 nanosecond. During this microsecond there may be as may as 72 data transfers.
SUMMARY OF THE INVENTION
In accordance with one feature of the invention, apparatus is provided for testing a system during operation of such system. The apparatus includes a generator for injecting an electrical disturbance into the system during operation of such system. The generator injects the electrical disturbance into the system in response to an actuation signal. A storage medium is provided for storing a state representative of a selected one of a plurality of operating states of the system. A comparator is provided for monitoring current operating state of the system. The comparator produces the activation signal when the current operating state of the system and the selected stored one of the plurality of operating states have a predetermined relationship.
In accordance with another feature of the invention, apparatus is provided for testing a system during operation of such system. The apparatus produces the disturbance from a source having an predetermined output impedance. The testing apparatus includes a buffer having drivers for transforming the output impedance of the source to a relatively low output impedance during injection of the disturbance while such drivers have a relatively high output impedance in the absence of the injection of the disturbance into the system to prevent current flow between the source and the system.
In one embodiment of the invention, the apparatus is adapted to inject the disturbances randomly in time into the system.
In accordance with still another feature of the invention, apparatus is provided for testing a system operating asynchronously. The testing apparatus includes a generator for injecting an electrical disturbance into the system during the asynchronous operation of such system. The generator injects the disturbance into the system in response to an actuation signal. A storage medium is provided for storing a determined state representative of a selected one of a plurality of operating states of the system. A comparator is provided for monitoring current operating state of the system. The comparator produces the activation signal when the current operating state of the system and the selected stored one of the plurality of operating states have a predetermined relationship to thereby synchronize the disturbance to the asynchronously operating system.
In accordance with still another feature of the invention, apparatus is provided for testing an interface used in a data storage system during operation of the interface. The interface is adapted for disposition between a host computer section having host computer system processors for processing data and a bank of disk drives. The interface has a controller and an addressable memory interconnected through a bus. The interface operates asynchronously in transferring data between the controller
Abramov Ron
Donnellan Mary T.
Backer Firmin
Daly, Crowley & Mofford LLP
EMC Corporation
Wiley David
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