Non-volatile semiconductor memory device having multiple...

Details Non-volatile semiconductor memory device having multiple... Non-volatile semiconductor memory device having multiple...

1998-07-31

2001-02-13

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S211000, C438S257000, C438S283000, C365S185030

Reexamination Certificate

active

06188102

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, particularly to a floating gate type non-volatile semiconductor memory device.
2. Description of the Related Art
FIG.
1
(
a
) is a plan view showing a constitution of a conventional non-volatile semiconductor memory device, FIG.
1
(
b
)is an enlarged section view taken along the line X—X in FIG.
1
(
a
), and FIG.
1
(
c
) is an enlarged section view taken along the line Y—Y in FIG.
1
(
a
), respectively.
As a non-volatile semiconductor memory device which is capable of writing and erasing data, an Electrically Erasable Programmable ROM (FLASH MEMORY) (hereinafter, referred to as an EPROM) has been heretofore known, which is a field effect transistor wherein a first gate insulating film is arranged on a channel region formed between source and drain regions on a surface of a semiconductor substrate, and a control gate capacitively coupled to a floating gate via a second gate insulating film is formed thereon.
This conventional semiconductor memory device stores the difference between threshold voltages in accordance with the difference between charge storage states in the floating gate in the form of “0” and “1” of data.
As shown in FIGS.
1
(
a
),
1
(
b
), and
1
(
c
), source and drain regions
1
and
2
are formed on a surface of a P-type semiconductor substrate
7
, and a first insulating film
8
, a floating gate
51
, a second insulating film
9
, and a control gate
5
are sequentially formed on a channel region formed between the source and drain regions
1
and
2
. An element is electrically isolated from other adjacent elements by the second insulating film
9
serving as a field oxide film. A polycrystalline silicon to which phosphorus is introduced is ordinarily used as the floating gate
51
. In this embodiment, cells adjacent to each other in the vertical direction share the source and drain regions
1
and
2
, as shown in FIG.
1
(
a
), and they use the source and drain regions
1
and
2
also as wirings. The source and drain regions
1
and
2
are separated from the floating-gate
51
by a fourth insulating film
13
.
In order to increase an integration density in such floating gate type non-volatile semiconductor memory device, reductions in a gate length of the floating gate and an interval between memory cells have been intended. Furthermore, to achieve this object, an exposing to form the floating gate has been carried out using a reduction projection exposing apparatus.
Even when the exposing is carried out by the above mentioned reduction projection exposing apparatus, however, since there is a limitation to the reduction of the gate length of the floating gate and the interval between the memory cells because of the inherent limitation due to a resolution of the reduction exposing projection apparatus, there is a limitation to the increase in the integration density of the floating gate type non-volatile semiconductor memory device. Therefore, there is a minimum dimension determined by the limitation to the resolution of such reduction exposing projection apparatus.
The memory cell, adjacent to another memory cell along the direction perpendicular to the axis connecting the source and drain regions, is separated from the other memory cells by a distance determined the minimum dimension described. To express two states “0” and “1” of data, the width of the memory cell and the width of the separation region between the memory cells are necessary and each memory cells and separation region must be more than the minimum dimension. For this reason, the memory structure expressing two data states “0” and “1”, covers a width twice the minimum dimension, when viewed along the line perpendicular to the axis connecting the source and drain regions.
SUMMARY OF THE INVENTION
As long as the foregoing memory structure is used, however, the integration density of the memory device is limited by the minimum dimension determined by manufacturing processes so that it is impossible to respond to requirements for higher integration density.
The object of the present invention is to provide a non-volatile semiconductor memory device having the structure which reduces the occupied area per the foregoing two states and increases the integration density of the semiconductor memory device.
To solve the foregoing subjects, in a non-volatile semiconductor memory device which comprises a semiconductor substrate having a major surface of P type; source and drain regions of N type formed in the major surface of the semiconductor substrate; a channel region formed between the source and drain regions; and a first insulating film, a floating gate, a second insulating film, and a control gate sequentially formed on the channel region, the improvement lies in the floating gate which consists of first and second floating gates. The under surfaces of the first and second floating gates contact the first insulating film and the upper surfaces of the first and second floating gates contact the second insulating film.
Furthermore, it should be desirable that a third insulating film electrically separates the first and second floating gates, the third insulating film is located so that each of channels is able to connect electrically between the source and drain regions, each of the channels located on each surface of the semiconductor substrate below the first floating gate and the second floating gate.
To achieve the foregoing object, in the non-volatile semiconductor memory device of the present invention, one memory cell has two floating gates, and one control gate controls these two floating gates. Each of the two floating gates is able to express the two states according to the existences of stored charges, so that one memory cell can express four states. The two floating gates are separated by an insulating film, and a sufficiently thin insulating film to insulate the two floating-gates in accordance with a minimum dimension determined by manufacturing process conditions. Since the width of the control gate and the interval between the adjacent memory cells can be reduced to the minimum dimension, one memory cell covers an area twice the minimum dimension. This fact proves that the non-volatile semiconductor memory cell of the present invention covers the area twice the minimum dimension to store the four values. Thus, the non-volatile semiconductor memory device of the present invention can obtain an integration density of the conventional memory cell.
In the non-volatile semiconductor memory device of the present invention, each of the two floating gates is able to express two states in accordance with the existence of stored charges in each of the floating gates. In order that the two floating gates are controlled with one control gate, four states are stored by one memory cell, and these four states are read out, the non-volatile semiconductor memory device of the present invention adopts the following structure and the following operation method.
Data writing is carried out using a channel hot electron method. In this method, when a positive voltage is applied to either the drain region or the source region and the gate, a region of a high electric field is produced near either the drain region or the source region. Among the accerelated electrons in this area, electrons which have sufficient energy (hot electrons) exceed a potential barrier of the tunnel film, and are injected to the floating gate. In order to produce the high electric field near either the drain region or the source region and to inject the hot electrons to the floating gate with a high effectiveness, a p
+
region having an impurity concentration higher than another channel region is formed.
In the non-volatile semiconductor memory device of the present invention, the writing operation requires that injections of charges to the first and second floating gates must be performed independently from each other. For this reason, regions having higher impurity concentration

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