Method to simulataneously fabricate the self-aligned silicided d

Details Method to simulataneously fabricate the self-aligned silicided d Method to simulataneously fabricate the self-aligned silicided d

1998-01-28

2000-05-16

Nguyen, Tuan H.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

306197, H01L 2144

Patent

active

060637064

ABSTRACT:
A method to simultaneously fabricate the self-aligned silicided devices and electrostatic discharge devices is disclosed. A substrate is provided, a functional region and an electrostatic discharge region are defined on the substrate, gates of the regions are formed, lightly doping drain is formed in the substrate, a pad silicon nitride is formed on the electrostatic discharge region, spacers of the functional region is formed, a refractory metal is deposited or sputtered on the functional region, a two-step salicide process is performed on the substrate and a salicide layer is formed on the surface of the functional region, a high-energy implantation is performed on the substrate to form the active regions of the functional device and the electrostatic discharge device, a thick field oxide is formed on the surface of the substrate and a rapid thermal processing anneal is performed on the substrate to form an ultra-shallow junction of the functional devices.

REFERENCES:
patent: 5262344 (1993-11-01), Mistry
patent: 5920774 (1999-07-01), Wu
Bin-Shing Chen et al., Formation of Cobalt Silicided Shallow Junction Using IMplant Into/Through Silicide Technology and Low Temperature Furnace Annealing, IEEE Transactions on Electron Devices, vol. 43, No. 2, Feb. 1996, pp. 258-266.
Kueing-Long Chen, Effects of Interconnect Process and Snapback Voltage on the ESD Failure Threshold of NMOS Transistors, 1988 EOS/ESD Symposium Proceedings, pp. 212-219.
Ajith Amerasekera et al., Correlating Drain Junction Scaling, Salicide Thickness, and Lateral NPN Behavior, with the ESD/EOS Performance of a 0.25 .mu.m CMOS Process, 1996 IEEE, pp. 893-896.
P. Fornara et al., Modeling of Local Reduction in TiSi.sub.2 Growth Near Spacers in MOS Technologies: Influence of Mechanical Stress and Main Diffusing Species, 1996 IEEE, pp. 73-76.

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