Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-09-02
2001-11-06
Mintel, William (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S344000, C257S401000, C257S408000, C257S900000, C438S301000, C438S304000, C438S306000, C438S491000
Reexamination Certificate
active
06313505
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductor fabrication, and more particularly to methods for fabricating improved ultra-large scale integration (ULSI) semiconductor devices such as ULSI metal oxide silicon field effect transistors (MOSFETs).
BACKGROUND OF THE INVENTION
Semiconductor chips or wafers are used in many applications, including as processor chips for computers, and as integrated circuits and as flash memory for hand held computing devices, wireless telephones, and digital cameras. Regardless of the application, it is desirable that a semiconductor chip hold as many circuits or memory cells as possible per unit area. In this way, the size, weight, and energy consumption of devices that use semiconductor chips advantageously is minimized, while nevertheless improving the memory capacity and computing power of the devices.
A common circuit component of semiconductor chips is the transistor. In ULSI semiconductor chips, a transistor is established by forming a polysilicon gate on a silicon substrate, and then forming a source region and a drain region side by side in the substrate beneath the gate by implanting appropriate dopant materials into the areas of the substrate that are to become the source and drain regions. The gate is insulated from the source and drain regions by a thin gate oxide layer, with small portions of the source and drain regions, referred to as “extensions”, directly underlying the gate. This generally-described structure cooperates to function as a transistor.
As the dimensions of MOSFETs desirably are reduced as discussed above, it will be readily appreciated that the depth to which the source and drain extensions of a transistor penetrates the silicon substrate decreases. Unfortunately, very shallow source/drain extensions are characterized by relatively high series resistances measured laterally across the extensions (i.e., measured in a dimension that is orthogonal to the depth of the extension in the substrate), which is a major cause of drive current degradation in ULSI transistors. Moreover, the shallow extensions increase the difficulty of forming otherwise desirable silicide in the source and drain regions.
To address the above-noted problem, elevated source and drain regions that are formed next to the gate on top of the substrate have been proposed. The elevated source and drain structures, however, have heretofore been formed by epitaxy, which is a high temperature process for depositing pure silicon on the substrate to establish the elevated source and drain regions. Indeed, epitaxy typically requires a deposition temperature of in excess of 1100° C. As recognized herein, the use of such a high temperature degrades the profiles of dopant implants and, hence, degrades transistor performance. Further, epitaxy is an expensive process to undertake. The present invention recognizes and addresses one or more of the above-noted problems.
BRIEF SUMMARY OF THE INVENTION
A method is disclosed for establishing at least one transistor on a semiconductor device. The method includes forming a gate on a semiconductor substrate, and depositing at least one protective layer on the gate. At least one dopant substance is pre-implanted into the substrate, with the protective layer substantially preventing implanting of the dopant substance through the layer into the gate. As intended by the present invention, the pre-implanting of the dopant substance promotes subsequent formation of source and drain extensions. Then, elevated source and drain regions are formed on the substrate adjacent the gate, and at least the elevated source and drain regions are implanted with at least one dopant substance to establish the transistor.
In a preferred embodiment, at least one sidewall spacer is established on the gate prior to the pre-implanting step, and at least one amorphization substance is implanted into the substrate prior to the pre-implanting step. The protective layer substantially prevents implanting the amorphization substance through the layer into the gate. Preferably, the protective layer is then removed from the gate prior to implanting the elevated source and drain regions with dopant, such that at least one dopant substance is implanted into the gate when the elevated source and drain regions are implanted with dopant.
As disclosed in detail below, the method can further include rapidly thermally annealing at least the elevated source and drain regions after implanting the elevated source and drain regions with dopant. This establishes source and drain extension regions in the substrate, which is promoted by the pre-implanting of dopant and amorphization substance. The gate and the elevated source and drain regions are then silicidized.
To minimize the temperature to which the device is subjected during fabrication, the elevated source and drain regions are formed by depositing one or more of polysilicon and polygermanium on the substrate. With this structure, the polysilicon/polygermanium is deposited at a temperature of no more than one thousand degrees Celsius (1000° C.), and indeed can be deposited at a temperature of about six hundred degrees Celsius (600° C.). A semiconductor device made according to the present method, and a digital processing apparatus incorporating the device, are also disclosed.
In another aspect, a method for making an ultra-large scale integration (ULSI) semiconductor device includes forming at least one gate on at least one semiconductor substrate, and forming elevated source and drain regions above the substrate by depositing at least one poly-semiconductor substance on the substrate.
In still another aspect, a semiconductor device includes at least one transistor. In turn, the transistor includes a gate disposed on a silicon substrate and elevated source and drain regions on the substrate next to the gate. In accordance with the present invention, the source and drain regions include at least polysilicon and/or polygermanium.
Other features of the present invention are disclosed or apparent in the section entitled “DETAILED DESCRIPTION OF THE INVENTION”.
REFERENCES:
patent: 5012306 (1991-04-01), Tasch, Jr. et al.
patent: 5559357 (1996-09-01), Krivokapic
patent: 5780896 (1998-07-01), Ouo
patent: 5998835 (1999-12-01), Furukawa et al.
patent: 6025635 (2000-02-01), Krivokapic
patent: 6049107 (2000-04-01), Peidous
Advanced Micro Devices , Inc.
LaRiviere Grubman & Payne, LLP
Mintel William
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